Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src implement cpuctl identify for sparc and sparc64.
details: https://anonhg.NetBSD.org/src/rev/c0aa9d11e142
branches: trunk
changeset: 829073:c0aa9d11e142
user: mrg <mrg%NetBSD.org@localhost>
date: Tue Jan 16 08:23:17 2018 +0000
description:
implement cpuctl identify for sparc and sparc64.
sparc:
- move enum vactype and struct cacheinfo into cpu.h
- move the cache flags from cpuinfo.flags into CACHEINFO.c_flags
(this allows the new cache_printf_backend() to see them.)
remove unused CPUFLG_CACHEIOMMUTABLES and CPUFLG_CACHEDVMA.
- align xmpsg to 64 bytes
- move cache_print() into cache_print.h so it can be shared with
cpuctl. it only depends upon a working printf().
- if found, store the CPU node's "name" into cpu_longname. this
changes the default output to show the local CPU not the
generic CPU family. eg:
cpu0 at mainbus0: mid 8: Ross,RT625 @ 90 MHz, on-chip FPU
vs the generic "RT620/625" previously shown.
- for each CPU export these things:
- name
- fpuname
- mid
- cloc
- freq
- psr impl and version
- mmu impl, version, and number of contexts
- cacheinfo structure (which changed for the first time ever
with this commit.)
sparc64:
- add a minimal "cacheinfo" structure to export the i/d/e-cache
size and linesize.
- store %ver, cpu node "name" and cacheinfo in cpu_info.
- set cpu_info ver, name and cacheinfo in cpu_attach(), and
export them via sysctl, as well as CPU ID and clock freq
cpuctl:
- add identifycpu_bind() that returns false on !x86 as their
identify routines do not need to run on a particular CPU to
obtain its information, and use it to avoid trying to set
affinity when not needed.
- add sparc and sparc64 cpu identify support using the newly
exported values.
diffstat:
sys/arch/sparc/include/cpu.h | 72 +++++++++++++++++-
sys/arch/sparc/sparc/cache.c | 8 +-
sys/arch/sparc/sparc/cache.h | 53 +--------------
sys/arch/sparc/sparc/cache_print.h | 87 ++++++++++++++++++++++++
sys/arch/sparc/sparc/cpu.c | 134 +++++++++++++++++++++---------------
sys/arch/sparc/sparc/cpuvar.h | 8 +-
sys/arch/sparc/sparc/pmap.c | 16 ++--
sys/arch/sparc64/include/cpu.h | 20 +++++-
sys/arch/sparc64/sparc64/cpu.c | 75 +++++++++++++++++++-
usr.sbin/cpuctl/arch/arm.c | 11 ++-
usr.sbin/cpuctl/arch/i386.c | 11 ++-
usr.sbin/cpuctl/arch/noarch.c | 11 ++-
usr.sbin/cpuctl/arch/sparc.c | 100 +++++++++++++++++++++++++++
usr.sbin/cpuctl/arch/sparc64.c | 129 +++++++++++++++++++++++++++++++++++
usr.sbin/cpuctl/cpuctl.c | 7 +-
usr.sbin/cpuctl/cpuctl.h | 3 +-
16 files changed, 596 insertions(+), 149 deletions(-)
diffs (truncated from 1212 to 300 lines):
diff -r 130a85ec41a0 -r c0aa9d11e142 sys/arch/sparc/include/cpu.h
--- a/sys/arch/sparc/include/cpu.h Tue Jan 16 08:15:29 2018 +0000
+++ b/sys/arch/sparc/include/cpu.h Tue Jan 16 08:23:17 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.99 2017/12/02 00:48:04 macallan Exp $ */
+/* $NetBSD: cpu.h,v 1.100 2018/01/16 08:23:17 mrg Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -56,6 +56,67 @@
* Exported definitions unique to SPARC cpu support.
*/
+/*
+ * Sun-4 and Sun-4c virtual address cache.
+ *
+ * Sun-4 virtual caches come in two flavors, write-through (Sun-4c)
+ * and write-back (Sun-4). The write-back caches are much faster
+ * but require a bit more care.
+ *
+ * This is exported via sysctl so be careful changing it.
+ */
+enum vactype { VAC_UNKNOWN, VAC_NONE, VAC_WRITETHROUGH, VAC_WRITEBACK };
+
+/*
+ * Cache control information.
+ *
+ * This is exported via sysctl so be careful changing it.
+ */
+
+struct cacheinfo {
+ int c_totalsize; /* total size, in bytes */
+ /* if split, MAX(icache,dcache) */
+ int c_enabled; /* true => cache is enabled */
+ int c_hwflush; /* true => have hardware flush */
+ int c_linesize; /* line size, in bytes */
+ /* if split, MIN(icache,dcache) */
+ int c_l2linesize; /* log2(linesize) */
+ int c_nlines; /* precomputed # of lines to flush */
+ int c_physical; /* true => cache has physical
+ address tags */
+ int c_associativity; /* # of "buckets" in cache line */
+ int c_split; /* true => cache is split */
+
+ int ic_totalsize; /* instruction cache */
+ int ic_enabled;
+ int ic_linesize;
+ int ic_l2linesize;
+ int ic_nlines;
+ int ic_associativity;
+
+ int dc_totalsize; /* data cache */
+ int dc_enabled;
+ int dc_linesize;
+ int dc_l2linesize;
+ int dc_nlines;
+ int dc_associativity;
+
+ int ec_totalsize; /* external cache info */
+ int ec_enabled;
+ int ec_linesize;
+ int ec_l2linesize;
+ int ec_nlines;
+ int ec_associativity;
+
+ enum vactype c_vactype;
+
+ int c_flags;
+#define CACHE_PAGETABLES 0x1 /* caching pagetables OK on (sun4m) */
+#define CACHE_TRAPPAGEBUG 0x2 /* trap page can't be cached (sun4) */
+#define CACHE_MANDATORY 0x4 /* if cache is on, don't use
+ uncached access */
+};
+
/* Things needed by crash or the kernel */
#if defined(_KERNEL) || defined(_KMEMUSER)
@@ -74,9 +135,6 @@
#if defined(_KERNEL)
#include <sparc/sparc/cpuvar.h>
#include <sparc/sparc/intreg.h>
-#else
-#include <arch/sparc/sparc/vaddrs.h>
-#include <arch/sparc/sparc/cache.h>
#endif
struct trapframe;
@@ -123,9 +181,9 @@
/*
* Primary Inter-processor message area. Keep this aligned
* to a cache line boundary if possible, as the structure
- * itself is one (normal 32 byte) cache-line.
+ * itself is one or less (32/64 byte) cache-line.
*/
- struct xpmsg msg __aligned(32);
+ struct xpmsg msg __aligned(64);
/* Scheduler flags */
int ci_want_ast;
@@ -149,7 +207,7 @@
paddr_t ctx_tbl_pa; /* [4m] ctx table physical address */
/* Cache information */
- struct cacheinfo cacheinfo; /* see cache.h */
+ struct cacheinfo cacheinfo; /* see above */
/* various flags to workaround anomalies in chips */
volatile int flags; /* see CPUFLG_xxx, below */
diff -r 130a85ec41a0 -r c0aa9d11e142 sys/arch/sparc/sparc/cache.c
--- a/sys/arch/sparc/sparc/cache.c Tue Jan 16 08:15:29 2018 +0000
+++ b/sys/arch/sparc/sparc/cache.c Tue Jan 16 08:23:17 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.c,v 1.99 2018/01/15 21:25:25 mrg Exp $ */
+/* $NetBSD: cache.c,v 1.100 2018/01/16 08:23:17 mrg Exp $ */
/*
* Copyright (c) 1996
@@ -59,7 +59,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.99 2018/01/15 21:25:25 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.100 2018/01/16 08:23:17 mrg Exp $");
#include "opt_multiprocessor.h"
#include "opt_sparc_arch.h"
@@ -166,7 +166,7 @@
* MS1 cache is write-through and not write-allocate, so we can
* use cacheable access while not displacing cache lines.
*/
- cpuinfo.flags |= CPUFLG_CACHE_MANDATORY;
+ CACHEINFO.c_flags |= CACHE_MANDATORY;
}
void
@@ -197,7 +197,7 @@
/* Set external cache enable bit in MXCC control register */
stda(MXCC_CTRLREG, ASI_CONTROL,
ldda(MXCC_CTRLREG, ASI_CONTROL) | MXCC_CTRLREG_CE);
- cpuinfo.flags |= CPUFLG_CACHEPAGETABLES; /* Ok to cache PTEs */
+ CACHEINFO.c_flags |= CACHE_PAGETABLES; /* Ok to cache PTEs */
CACHEINFO.ec_enabled = 1;
}
}
diff -r 130a85ec41a0 -r c0aa9d11e142 sys/arch/sparc/sparc/cache.h
--- a/sys/arch/sparc/sparc/cache.h Tue Jan 16 08:15:29 2018 +0000
+++ b/sys/arch/sparc/sparc/cache.h Tue Jan 16 08:23:17 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.h,v 1.35 2007/03/04 06:00:45 christos Exp $ */
+/* $NetBSD: cache.h,v 1.36 2018/01/16 08:23:17 mrg Exp $ */
/*
* Copyright (c) 1996
@@ -51,16 +51,6 @@
#endif
/*
- * Sun-4 and Sun-4c virtual address cache.
- *
- * Sun-4 virtual caches come in two flavors, write-through (Sun-4c)
- * and write-back (Sun-4). The write-back caches are much faster
- * but require a bit more care.
- *
- */
-enum vactype { VAC_UNKNOWN, VAC_NONE, VAC_WRITETHROUGH, VAC_WRITEBACK };
-
-/*
* Cache tags can be written in control space, and must be set to 0
* (or invalid anyway) before turning on the cache. The tags are
* addressed as an array of 32-bit structures of the form:
@@ -234,47 +224,6 @@
#define pcache_flush_page(pa,flag) cpuinfo.pcache_flush_page(pa,flag)
-/*
- * Cache control information.
- */
-struct cacheinfo {
- int c_totalsize; /* total size, in bytes */
- /* if split, MAX(icache,dcache) */
- int c_enabled; /* true => cache is enabled */
- int c_hwflush; /* true => have hardware flush */
- int c_linesize; /* line size, in bytes */
- /* if split, MIN(icache,dcache) */
- int c_l2linesize; /* log2(linesize) */
- int c_nlines; /* precomputed # of lines to flush */
- int c_physical; /* true => cache has physical
- address tags */
- int c_associativity; /* # of "buckets" in cache line */
- int c_split; /* true => cache is split */
-
- int ic_totalsize; /* instruction cache */
- int ic_enabled;
- int ic_linesize;
- int ic_l2linesize;
- int ic_nlines;
- int ic_associativity;
-
- int dc_totalsize; /* data cache */
- int dc_enabled;
- int dc_linesize;
- int dc_l2linesize;
- int dc_nlines;
- int dc_associativity;
-
- int ec_totalsize; /* external cache info */
- int ec_enabled;
- int ec_linesize;
- int ec_l2linesize;
- int ec_nlines;
- int ec_associativity;
-
- enum vactype c_vactype;
-};
-
#define CACHEINFO cpuinfo.cacheinfo
#endif /* SPARC_CACHE_H */
diff -r 130a85ec41a0 -r c0aa9d11e142 sys/arch/sparc/sparc/cache_print.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/sparc/sparc/cache_print.h Tue Jan 16 08:23:17 2018 +0000
@@ -0,0 +1,87 @@
+/* $NetBSD: cache_print.h,v 1.1 2018/01/16 08:23:17 mrg Exp $ */
+
+/*-
+ * Copyright (c) 1997 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Paul Kranenburg.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This works for kernel and cpuctl(8). It only relies upon having
+ * a working printf() in the environment.
+ */
+
+static void cache_printf_backend(struct cacheinfo *ci, const char *cpuname);
+
+static void
+cache_printf_backend(struct cacheinfo *ci, const char *cpuname)
+{
+
+ if (ci->c_flags & CACHE_TRAPPAGEBUG)
+ printf("%s: cache chip bug; trap page uncached\n", cpuname);
+
+ printf("%s: ", cpuname);
+
+ if (ci->c_totalsize == 0) {
+ printf("no cache\n");
+ return;
+ }
+
+ if (ci->c_split) {
+ const char *sep = "";
+
+ printf("%s", (ci->c_physical ? "physical " : ""));
+ if (ci->ic_totalsize > 0) {
+ printf("%s%dK instruction (%d b/l)", sep,
+ ci->ic_totalsize/1024, ci->ic_linesize);
+ sep = ", ";
+ }
+ if (ci->dc_totalsize > 0) {
+ printf("%s%dK data (%d b/l)", sep,
+ ci->dc_totalsize/1024, ci->dc_linesize);
+ }
+ } else if (ci->c_physical) {
+ /* combined, physical */
+ printf("physical %dK combined cache (%d bytes/line)",
+ ci->c_totalsize/1024, ci->c_linesize);
+ } else {
+ /* combined, virtual */
+ printf("%dK byte write-%s, %d bytes/line, %cw flush",
+ ci->c_totalsize/1024,
+ (ci->c_vactype == VAC_WRITETHROUGH) ? "through" : "back",
+ ci->c_linesize,
+ ci->c_hwflush ? 'h' : 's');
+ }
+
Home |
Main Index |
Thread Index |
Old Index