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[src/trunk]: src/sys/dev/ic Cleanup and __BIT()ify
details: https://anonhg.NetBSD.org/src/rev/e6122baa7046
branches: trunk
changeset: 802437:e6122baa7046
user: martin <martin%NetBSD.org@localhost>
date: Sun Sep 14 11:00:52 2014 +0000
description:
Cleanup and __BIT()ify
diffstat:
sys/dev/ic/dwc_gmac.c | 104 ++++++++++++++++++++++++---------------
sys/dev/ic/dwc_gmac_reg.h | 118 +++++++++++++++++++++++++--------------------
2 files changed, 128 insertions(+), 94 deletions(-)
diffs (truncated from 371 to 300 lines):
diff -r 3a4d68e8f76b -r e6122baa7046 sys/dev/ic/dwc_gmac.c
--- a/sys/dev/ic/dwc_gmac.c Sun Sep 14 09:34:12 2014 +0000
+++ b/sys/dev/ic/dwc_gmac.c Sun Sep 14 11:00:52 2014 +0000
@@ -39,7 +39,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: dwc_gmac.c,v 1.5 2014/09/11 06:56:05 martin Exp $");
+__KERNEL_RCSID(1, "$NetBSD: dwc_gmac.c,v 1.6 2014/09/14 11:00:52 martin Exp $");
#include "opt_inet.h"
@@ -244,16 +244,17 @@
dwc_gmac_miibus_read_reg(device_t self, int phy, int reg)
{
struct dwc_gmac_softc * const sc = device_private(self);
- uint16_t miiaddr;
+ uint16_t mii;
size_t cnt;
int rv = 0;
- miiaddr = ((phy << GMAC_MII_PHY_SHIFT) & GMAC_MII_PHY_MASK)
- | ((reg << GMAC_MII_REG_SHIFT) & GMAC_MII_REG_MASK);
+ mii = __SHIFTIN(phy,GMAC_MII_PHY_MASK)
+ | __SHIFTIN(reg,GMAC_MII_REG_MASK)
+ | __SHIFTIN(sc->sc_mii_clk,GMAC_MII_CLKMASK)
+ | GMAC_MII_BUSY;
mutex_enter(&sc->sc_mdio_lock);
- bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_MIIADDR,
- miiaddr | GMAC_MII_BUSY | (sc->sc_mii_clk << 2));
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_MIIADDR, mii);
for (cnt = 0; cnt < 1000; cnt++) {
if (!(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
@@ -274,17 +275,17 @@
dwc_gmac_miibus_write_reg(device_t self, int phy, int reg, int val)
{
struct dwc_gmac_softc * const sc = device_private(self);
- uint16_t miiaddr;
+ uint16_t mii;
size_t cnt;
- miiaddr = ((phy << GMAC_MII_PHY_SHIFT) & GMAC_MII_PHY_MASK)
- | ((reg << GMAC_MII_REG_SHIFT) & GMAC_MII_REG_MASK)
- | GMAC_MII_BUSY | GMAC_MII_WRITE | (sc->sc_mii_clk << 2);
+ mii = __SHIFTIN(phy,GMAC_MII_PHY_MASK)
+ | __SHIFTIN(reg,GMAC_MII_REG_MASK)
+ | __SHIFTIN(sc->sc_mii_clk,GMAC_MII_CLKMASK)
+ | GMAC_MII_BUSY | GMAC_MII_WRITE;
mutex_enter(&sc->sc_mdio_lock);
bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_MIIDATA, val);
- bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_MIIADDR,
- miiaddr);
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_MIIADDR, mii);
for (cnt = 0; cnt < 1000; cnt++) {
if (!(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
@@ -302,8 +303,7 @@
{
struct dwc_gmac_rx_data *data;
bus_addr_t physaddr;
- const size_t descsize =
- AWGE_RX_RING_COUNT * sizeof(*ring->r_desc);
+ const size_t descsize = AWGE_RX_RING_COUNT * sizeof(*ring->r_desc);
int error, i, next;
ring->r_cur = ring->r_next = 0;
@@ -352,12 +352,11 @@
desc = &sc->sc_rxq.r_desc[i];
desc->ddesc_data = htole32(physaddr);
- next = i < (AWGE_RX_RING_COUNT-1) ? i+1 : 0;
+ next = (i+1) & AWGE_RX_RING_COUNT;
desc->ddesc_next = htole32(ring->r_physaddr
+ next * sizeof(*desc));
desc->ddesc_cntl = htole32(
- (AWGE_MAX_PACKET & DDESC_CNTL_SIZE1MASK)
- << DDESC_CNTL_SIZE1SHIFT);
+ __SHIFTIN(AWGE_MAX_PACKET,DDESC_CNTL_SIZE1MASK));
desc->ddesc_status = htole32(DDESC_STATUS_OWNEDBYDEV);
}
@@ -365,7 +364,7 @@
AWGE_RX_RING_COUNT*sizeof(struct dwc_gmac_dev_dmadesc),
BUS_DMASYNC_PREREAD);
bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RX_ADDR,
- htole32(ring->r_physaddr));
+ ring->r_physaddr);
return 0;
@@ -384,8 +383,7 @@
for (i = 0; i < AWGE_RX_RING_COUNT; i++) {
desc = &sc->sc_rxq.r_desc[i];
desc->ddesc_cntl = htole32(
- (AWGE_MAX_PACKET & DDESC_CNTL_SIZE1MASK)
- << DDESC_CNTL_SIZE1SHIFT);
+ __SHIFTIN(AWGE_MAX_PACKET,DDESC_CNTL_SIZE1MASK));
desc->ddesc_status = htole32(DDESC_STATUS_OWNEDBYDEV);
}
@@ -574,6 +572,8 @@
TX_DESC_OFFSET(0),
AWGE_TX_RING_COUNT*sizeof(struct dwc_gmac_dev_dmadesc),
BUS_DMASYNC_PREWRITE);
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_TX_ADDR,
+ sc->sc_txq.t_physaddr);
ring->t_queued = 0;
ring->t_cur = ring->t_next = 0;
@@ -639,9 +639,18 @@
dwc_gmac_stop(ifp, 0);
/*
- * Set up dma pointer for RX ring
+ * Set up dma pointer for RX and TX ring
*/
- bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RX_ADDR, sc->sc_rxq.r_physaddr);
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RX_ADDR,
+ sc->sc_rxq.r_physaddr);
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_TX_ADDR,
+ sc->sc_txq.t_physaddr);
+
+ /*
+ * Start RX part
+ */
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh,
+ AWIN_GMAC_DMA_OPMODE, GMAC_DMA_OP_RXSTART);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
@@ -675,9 +684,15 @@
/* packets have been queued, kick it off */
dwc_gmac_txdesc_sync(sc, old, sc->sc_txq.t_cur,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
- bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_TX_ADDR,
- sc->sc_txq.t_physaddr
- + old*sizeof(struct dwc_gmac_dev_dmadesc));
+
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh,
+ AWIN_GMAC_DMA_OPMODE,
+ bus_space_read_4(sc->sc_bst, sc->sc_bsh,
+ AWIN_GMAC_DMA_OPMODE) | GMAC_DMA_OP_FLUSHTX);
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh,
+ AWIN_GMAC_DMA_OPMODE,
+ bus_space_read_4(sc->sc_bst, sc->sc_bsh,
+ AWIN_GMAC_DMA_OPMODE) | GMAC_DMA_OP_TXSTART);
}
}
@@ -686,6 +701,16 @@
{
struct dwc_gmac_softc *sc = ifp->if_softc;
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh,
+ AWIN_GMAC_DMA_OPMODE,
+ bus_space_read_4(sc->sc_bst, sc->sc_bsh,
+ AWIN_GMAC_DMA_OPMODE)
+ & ~(GMAC_DMA_OP_TXSTART|GMAC_DMA_OP_RXSTART));
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh,
+ AWIN_GMAC_DMA_OPMODE,
+ bus_space_read_4(sc->sc_bst, sc->sc_bsh,
+ AWIN_GMAC_DMA_OPMODE) | GMAC_DMA_OP_FLUSHTX);
+
mii_down(&sc->sc_mii);
dwc_gmac_reset_tx_ring(sc, &sc->sc_txq);
dwc_gmac_reset_rx_ring(sc, &sc->sc_rxq);
@@ -700,7 +725,7 @@
struct dwc_gmac_dev_dmadesc *desc = NULL;
struct dwc_gmac_tx_data *data = NULL;
bus_dmamap_t map;
- uint32_t status, flags, len;
+ uint32_t flags, len;
int error, i, first;
first = sc->sc_txq.t_cur;
@@ -721,36 +746,33 @@
}
data = NULL;
- flags = DDESC_STATUS_TXINT|DDESC_STATUS_TXCHAIN;
+ flags = DDESC_CNTL_TXFIRST|DDESC_CNTL_TXINT|DDESC_CNTL_TXCHAIN;
for (i = 0; i < map->dm_nsegs; i++) {
data = &sc->sc_txq.t_data[sc->sc_txq.t_cur];
desc = &sc->sc_txq.t_desc[sc->sc_txq.t_cur];
desc->ddesc_data = htole32(map->dm_segs[i].ds_addr);
- len = (map->dm_segs[i].ds_len & DDESC_CNTL_SIZE1MASK)
- << DDESC_CNTL_SIZE1SHIFT;
- desc->ddesc_cntl = htole32(len);
- status = flags;
- desc->ddesc_status = htole32(status);
- sc->sc_txq.t_queued++;
+ len = __SHIFTIN(map->dm_segs[i].ds_len,DDESC_CNTL_SIZE1MASK);
+ if (i == map->dm_nsegs-1)
+ flags |= DDESC_CNTL_TXLAST;
+ desc->ddesc_cntl = htole32(len|flags);
+ flags &= ~DDESC_CNTL_TXFIRST;
/*
* Defer passing ownership of the first descriptor
* untill we are done.
*/
- flags |= DDESC_STATUS_OWNEDBYDEV;
+ if (i)
+ desc->ddesc_status = htole32(DDESC_STATUS_OWNEDBYDEV);
+ sc->sc_txq.t_queued++;
sc->sc_txq.t_cur = (sc->sc_txq.t_cur + 1)
& (AWGE_TX_RING_COUNT-1);
}
- /* Fixup last */
- status = flags|DDESC_STATUS_TXLAST;
- desc->ddesc_status = htole32(status);
-
- /* Finalize first */
- status = flags|DDESC_STATUS_TXFIRST;
- sc->sc_txq.t_desc[first].ddesc_status = htole32(status);
+ /* Pass first to device */
+ sc->sc_txq.t_desc[first].ddesc_status
+ = htole32(DDESC_STATUS_OWNEDBYDEV);
data->td_m = m0;
data->td_active = map;
diff -r 3a4d68e8f76b -r e6122baa7046 sys/dev/ic/dwc_gmac_reg.h
--- a/sys/dev/ic/dwc_gmac_reg.h Sun Sep 14 09:34:12 2014 +0000
+++ b/sys/dev/ic/dwc_gmac_reg.h Sun Sep 14 11:00:52 2014 +0000
@@ -56,32 +56,37 @@
#define AWIN_GMAC_DMA_CUR_RX_BUFADDR 0x1054
#define GMAC_MII_PHY_SHIFT 11
-#define GMAC_MII_PHY_MASK (0x1F << GMAC_MII_PHY_SHIFT)
+#define GMAC_MII_PHY_MASK __BITS(15,11)
#define GMAC_MII_REG_SHIFT 6
-#define GMAC_MII_REG_MASK (0x1F << GMAC_MII_REG_SHIFT)
+#define GMAC_MII_REG_MASK __BITS(10,6)
+
+#define GMAC_MII_BUSY __BIT(0)
+#define GMAC_MII_WRITE __BIT(1)
+#define GMAC_MII_CLKMASK __BITS(4,2)
-#define GMAC_MII_BUSY 1
-#define GMAC_MII_WRITE 2
+#define GMAC_BUSMODE_RESET __BIT(0)
+
+#define AWIN_GMAC_MII_IRQ __BIT(0)
-#define GMAC_BUSMODE_RESET 1
-
-#define AWIN_GMAC_MII_IRQ 1
+#define GMAC_DMA_OP_FLUSHTX __BIT(20)
+#define GMAC_DMA_OP_TXSTART __BIT(13)
+#define GMAC_DMA_OP_RXSTART __BIT(0)
-#define GMAC_DMA_INT_NIE 0x10000 /* Normal/Summary */
-#define GMAC_DMA_INT_AIE 0x08000 /* Abnormal/Summary */
-#define GMAC_DMA_INT_ERE 0x04000 /* Early receive */
-#define GMAC_DMA_INT_FBE 0x02000 /* Fatal bus error */
-#define GMAC_DMA_INT_ETE 0x00400 /* Early transmit */
-#define GMAC_DMA_INT_RWE 0x00200 /* Receive watchdog */
-#define GMAC_DMA_INT_RSE 0x00100 /* Receive stopped */
-#define GMAC_DMA_INT_RUE 0x00080 /* Receive buffer unavailable */
-#define GMAC_DMA_INT_RIE 0x00040 /* Receive interrupt */
-#define GMAC_DMA_INT_UNE 0x00020 /* Tx underflow */
-#define GMAC_DMA_INT_OVE 0x00010 /* Receive overflow */
-#define GMAC_DMA_INT_TJE 0x00008 /* Transmit jabber */
-#define GMAC_DMA_INT_TUE 0x00004 /* Transmit buffer unavailable */
-#define GMAC_DMA_INT_TSE 0x00002 /* Transmit stopped */
-#define GMAC_DMA_INT_TIE 0x00001 /* Transmit interrupt */
+#define GMAC_DMA_INT_NIE __BIT(16) /* Normal/Summary */
+#define GMAC_DMA_INT_AIE __BIT(15) /* Abnormal/Summary */
+#define GMAC_DMA_INT_ERE __BIT(14) /* Early receive */
+#define GMAC_DMA_INT_FBE __BIT(13) /* Fatal bus error */
+#define GMAC_DMA_INT_ETE __BIT(10) /* Early transmit */
+#define GMAC_DMA_INT_RWE __BIT(9) /* Receive watchdog */
+#define GMAC_DMA_INT_RSE __BIT(8) /* Receive stopped */
+#define GMAC_DMA_INT_RUE __BIT(7) /* Receive buffer unavailable */
+#define GMAC_DMA_INT_RIE __BIT(6) /* Receive interrupt */
+#define GMAC_DMA_INT_UNE __BIT(5) /* Tx underflow */
+#define GMAC_DMA_INT_OVE __BIT(4) /* Receive overflow */
+#define GMAC_DMA_INT_TJE __BIT(3) /* Transmit jabber */
+#define GMAC_DMA_INT_TUE __BIT(2) /* Transmit buffer unavailable */
+#define GMAC_DMA_INT_TSE __BIT(1) /* Transmit stopped */
+#define GMAC_DMA_INT_TIE __BIT(0) /* Transmit interrupt */
#define GMAC_DEF_DMA_INT_MASK (GMAC_DMA_INT_TIE|GMAC_DMA_INT_RIE| \
GMAC_DMA_INT_NIE|GMAC_DMA_INT_AIE| \
@@ -92,42 +97,49 @@
struct dwc_gmac_dev_dmadesc {
uint32_t ddesc_status;
/* both: */
-#define DDESC_STATUS_OWNEDBYDEV (1<<31)
-/* for TX descriptors */
-#define DDESC_STATUS_TXINT (1<<30)
-#define DDESC_STATUS_TXLAST (1<<29)
-#define DDESC_STATUS_TXFIRST (1<<28)
-#define DDESC_STATUS_TXCRCDIS (1<<27)
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