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[src/trunk]: src/sys/arch/sparc move struct cpu_info and xpmsg into <machine/...
details: https://anonhg.NetBSD.org/src/rev/351075e62f77
branches: trunk
changeset: 819553:351075e62f77
user: mrg <mrg%NetBSD.org@localhost>
date: Sat Dec 10 09:51:43 2016 +0000
description:
move struct cpu_info and xpmsg into <machine/cpu.h> from
<sparc/sparc/cpuvar.h>. this enables them for crash(8)
and this seems more natural to me anyway.
diffstat:
sys/arch/sparc/include/cpu.h | 267 +++++++++++++++++++++++++++++++++++++++++-
sys/arch/sparc/sparc/cpuvar.h | 258 +----------------------------------------
2 files changed, 267 insertions(+), 258 deletions(-)
diffs (truncated from 557 to 300 lines):
diff -r e3e862af3f5f -r 351075e62f77 sys/arch/sparc/include/cpu.h
--- a/sys/arch/sparc/include/cpu.h Sat Dec 10 09:49:00 2016 +0000
+++ b/sys/arch/sparc/include/cpu.h Sat Dec 10 09:51:43 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.95 2013/10/19 19:20:59 christos Exp $ */
+/* $NetBSD: cpu.h,v 1.96 2016/12/10 09:51:43 mrg Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -63,10 +63,275 @@
#include "opt_sparc_arch.h"
#endif
+#include <sys/cpu_data.h>
+#include <sys/evcnt.h>
+
#include <machine/intr.h>
#include <machine/psl.h>
+
+#if defined(_KERNEL)
#include <sparc/sparc/cpuvar.h>
#include <sparc/sparc/intreg.h>
+#else
+#include <arch/sparc/sparc/vaddrs.h>
+#include <arch/sparc/sparc/cache.h>
+#endif
+
+/*
+ * Message structure for Inter Processor Communication in MP systems
+ */
+struct xpmsg {
+ volatile int tag;
+#define XPMSG15_PAUSECPU 1
+#define XPMSG_FUNC 4
+#define XPMSG_FTRP 5
+
+ volatile union {
+ /*
+ * Cross call: ask to run (*func)(arg0,arg1,arg2)
+ * or (*trap)(arg0,arg1,arg2). `trap' should be the
+ * address of a `fast trap' handler that executes in
+ * the trap window (see locore.s).
+ */
+ struct xpmsg_func {
+ void (*func)(int, int, int);
+ void (*trap)(int, int, int);
+ int arg0;
+ int arg1;
+ int arg2;
+ } xpmsg_func;
+ } u;
+ volatile int received;
+ volatile int complete;
+};
+
+/*
+ * The cpuinfo structure. This structure maintains information about one
+ * currently installed CPU (there may be several of these if the machine
+ * supports multiple CPUs, as on some Sun4m architectures). The information
+ * in this structure supersedes the old "cpumod", "mmumod", and similar
+ * fields.
+ */
+
+struct cpu_info {
+ struct cpu_data ci_data; /* MI per-cpu data */
+
+ /*
+ * Primary Inter-processor message area. Keep this aligned
+ * to a cache line boundary if possible, as the structure
+ * itself is one (normal 32 byte) cache-line.
+ */
+ struct xpmsg msg __aligned(32);
+
+ /* Scheduler flags */
+ int ci_want_ast;
+ int ci_want_resched;
+
+ /*
+ * SPARC cpu_info structures live at two VAs: one global
+ * VA (so each CPU can access any other CPU's cpu_info)
+ * and an alias VA CPUINFO_VA which is the same on each
+ * CPU and maps to that CPU's cpu_info. Since the alias
+ * CPUINFO_VA is how we locate our cpu_info, we have to
+ * self-reference the global VA so that we can return it
+ * in the curcpu() macro.
+ */
+ struct cpu_info * volatile ci_self;
+
+ int ci_cpuid; /* CPU index (see cpus[] array) */
+
+ /* Context administration */
+ int *ctx_tbl; /* [4m] SRMMU-edible context table */
+ paddr_t ctx_tbl_pa; /* [4m] ctx table physical address */
+
+ /* Cache information */
+ struct cacheinfo cacheinfo; /* see cache.h */
+
+ /* various flags to workaround anomalies in chips */
+ volatile int flags; /* see CPUFLG_xxx, below */
+
+ /* Per processor counter register (sun4m only) */
+ volatile struct counter_4m *counterreg_4m;
+
+ /* Per processor interrupt mask register (sun4m only) */
+ volatile struct icr_pi *intreg_4m;
+ /*
+ * Send a IPI to (cpi). For Ross cpus we need to read
+ * the pending register to avoid a hardware bug.
+ */
+#define raise_ipi(cpi,lvl) do { \
+ int x; \
+ (cpi)->intreg_4m->pi_set = PINTR_SINTRLEV(lvl); \
+ x = (cpi)->intreg_4m->pi_pend; __USE(x); \
+} while (0)
+
+ int sun4_mmu3l; /* [4]: 3-level MMU present */
+#if defined(SUN4_MMU3L)
+#define HASSUN4_MMU3L (cpuinfo.sun4_mmu3l)
+#else
+#define HASSUN4_MMU3L (0)
+#endif
+ int ci_idepth; /* Interrupt depth */
+
+ /*
+ * The following pointers point to processes that are somehow
+ * associated with this CPU--running on it, using its FPU,
+ * etc.
+ */
+ struct lwp *ci_curlwp; /* CPU owner */
+ struct lwp *fplwp; /* FPU owner */
+
+ int ci_mtx_count;
+ int ci_mtx_oldspl;
+
+ /*
+ * Idle PCB and Interrupt stack;
+ */
+ void *eintstack; /* End of interrupt stack */
+#define INT_STACK_SIZE (128 * 128) /* 128 128-byte stack frames */
+ void *redzone; /* DEBUG: stack red zone */
+#define REDSIZE (8*96) /* some room for bouncing */
+
+ struct pcb *curpcb; /* CPU's PCB & kernel stack */
+
+ /* locore defined: */
+ void (*get_syncflt)(void); /* Not C-callable */
+ int (*get_asyncflt)(u_int *, u_int *);
+
+ /* Synchronous Fault Status; temporary storage */
+ struct {
+ int sfsr;
+ int sfva;
+ } syncfltdump;
+
+ /*
+ * Cache handling functions.
+ * Most cache flush function come in two flavours: one that
+ * acts only on the CPU it executes on, and another that
+ * uses inter-processor signals to flush the cache on
+ * all processor modules.
+ * The `ft_' versions are fast trap cache flush handlers.
+ */
+ void (*cache_flush)(void *, u_int);
+ void (*vcache_flush_page)(int, int);
+ void (*sp_vcache_flush_page)(int, int);
+ void (*ft_vcache_flush_page)(int, int);
+ void (*vcache_flush_segment)(int, int, int);
+ void (*sp_vcache_flush_segment)(int, int, int);
+ void (*ft_vcache_flush_segment)(int, int, int);
+ void (*vcache_flush_region)(int, int);
+ void (*sp_vcache_flush_region)(int, int);
+ void (*ft_vcache_flush_region)(int, int);
+ void (*vcache_flush_context)(int);
+ void (*sp_vcache_flush_context)(int);
+ void (*ft_vcache_flush_context)(int);
+
+ /* The are helpers for (*cache_flush)() */
+ void (*sp_vcache_flush_range)(int, int, int);
+ void (*ft_vcache_flush_range)(int, int, int);
+
+ void (*pcache_flush_page)(paddr_t, int);
+ void (*pure_vcache_flush)(void);
+ void (*cache_flush_all)(void);
+
+ /* Support for hardware-assisted page clear/copy */
+ void (*zero_page)(paddr_t);
+ void (*copy_page)(paddr_t, paddr_t);
+
+ /* Virtual addresses for use in pmap copy_page/zero_page */
+ void * vpage[2];
+ int *vpage_pte[2]; /* pte location of vpage[] */
+
+ void (*cache_enable)(void);
+
+ int cpu_type; /* Type: see CPUTYP_xxx below */
+
+ /* Inter-processor message area (high priority but used infrequently) */
+ struct xpmsg msg_lev15;
+
+ /* CPU information */
+ int node; /* PROM node for this CPU */
+ int mid; /* Module ID for MP systems */
+ int mbus; /* 1 if CPU is on MBus */
+ int mxcc; /* 1 if a MBus-level MXCC is present */
+ const char *cpu_longname; /* CPU model */
+ int cpu_impl; /* CPU implementation code */
+ int cpu_vers; /* CPU version code */
+ int mmu_impl; /* MMU implementation code */
+ int mmu_vers; /* MMU version code */
+ int master; /* 1 if this is bootup CPU */
+
+ vaddr_t mailbox; /* VA of CPU's mailbox */
+
+ int mmu_ncontext; /* Number of contexts supported */
+ int mmu_nregion; /* Number of regions supported */
+ int mmu_nsegment; /* [4/4c] Segments */
+ int mmu_npmeg; /* [4/4c] Pmegs */
+
+/* XXX - we currently don't actually use the following */
+ int arch; /* Architecture: CPU_SUN4x */
+ int class; /* Class: SuperSPARC, microSPARC... */
+ int classlvl; /* Iteration in class: 1, 2, etc. */
+ int classsublvl; /* stepping in class (version) */
+
+ int hz; /* Clock speed */
+
+ /* FPU information */
+ int fpupresent; /* true if FPU is present */
+ int fpuvers; /* FPU revision */
+ const char *fpu_name; /* FPU model */
+ char fpu_namebuf[32];/* Buffer for FPU name, if necessary */
+
+ /* XXX */
+ volatile void *ci_ddb_regs; /* DDB regs */
+
+ /*
+ * The following are function pointers to do interesting CPU-dependent
+ * things without having to do type-tests all the time
+ */
+
+ /* bootup things: access to physical memory */
+ u_int (*read_physmem)(u_int addr, int space);
+ void (*write_physmem)(u_int addr, u_int data);
+ void (*cache_tablewalks)(void);
+ void (*mmu_enable)(void);
+ void (*hotfix)(struct cpu_info *);
+
+
+#if 0
+ /* hardware-assisted block operation routines */
+ void (*hwbcopy)(const void *from, void *to, size_t len);
+ void (*hwbzero)(void *buf, size_t len);
+
+ /* routine to clear mbus-sbus buffers */
+ void (*mbusflush)(void);
+#endif
+
+ /*
+ * Memory error handler; parity errors, unhandled NMIs and other
+ * unrecoverable faults end up here.
+ */
+ void (*memerr)(unsigned, u_int, u_int, struct trapframe *);
+ void (*idlespin)(struct cpu_info *);
+ /* Module Control Registers */
+ /*bus_space_handle_t*/ long ci_mbusport;
+ /*bus_space_handle_t*/ long ci_mxccregs;
+
+ u_int ci_tt; /* Last trap (if tracing) */
+
+ /*
+ * Start/End VA's of this cpu_info region; we upload the other pages
+ * in this region that aren't part of the cpu_info to uvm.
+ */
+ vaddr_t ci_free_sva1, ci_free_eva1, ci_free_sva2, ci_free_eva2;
+
+ struct evcnt ci_savefpstate;
+ struct evcnt ci_savefpstate_null;
+ struct evcnt ci_xpmsg_mutex_fail;
+ struct evcnt ci_xpmsg_mutex_fail_call;
+ struct evcnt ci_intrcnt[16];
+ struct evcnt ci_sintrcnt[16];
+};
/*
* definitions of cpu-dependent requirements
diff -r e3e862af3f5f -r 351075e62f77 sys/arch/sparc/sparc/cpuvar.h
--- a/sys/arch/sparc/sparc/cpuvar.h Sat Dec 10 09:49:00 2016 +0000
+++ b/sys/arch/sparc/sparc/cpuvar.h Sat Dec 10 09:51:43 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuvar.h,v 1.92 2013/11/16 23:54:01 mrg Exp $ */
+/* $NetBSD: cpuvar.h,v 1.93 2016/12/10 09:51:43 mrg Exp $ */
/*
* Copyright (c) 1996 The NetBSD Foundation, Inc.
@@ -89,262 +89,6 @@
};
/*
- * Message structure for Inter Processor Communication in MP systems
- */
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