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[src/trunk]: src/sys/arch/mips Define COP0 register that use select value in ...
details: https://anonhg.NetBSD.org/src/rev/9d0b8c2acd1e
branches: trunk
changeset: 808910:9d0b8c2acd1e
user: matt <matt%NetBSD.org@localhost>
date: Sun Jun 07 08:03:10 2015 +0000
description:
Define COP0 register that use select value in <mips/cpuregs.h>
Use those new definitions
diffstat:
sys/arch/mips/include/cpuregs.h | 34 ++++++++++++++++++++++++++++++++--
sys/arch/mips/mips/locore.S | 4 ++--
sys/arch/mips/mips/locore_mips3.S | 12 ++++++------
sys/arch/mips/mips/locore_octeon.S | 10 +++++-----
sys/arch/mips/mips/mipsX_subr.S | 4 ++--
sys/arch/mips/rmi/rmixl_subr.S | 12 ++++++------
6 files changed, 53 insertions(+), 23 deletions(-)
diffs (230 lines):
diff -r dc7f8d4bc748 -r 9d0b8c2acd1e sys/arch/mips/include/cpuregs.h
--- a/sys/arch/mips/include/cpuregs.h Sun Jun 07 07:19:21 2015 +0000
+++ b/sys/arch/mips/include/cpuregs.h Sun Jun 07 08:03:10 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.91 2015/06/01 22:55:12 matt Exp $ */
+/* $NetBSD: cpuregs.h,v 1.92 2015/06/07 08:03:10 matt Exp $ */
/*
* Copyright (c) 2009 Miodrag Vallat.
@@ -494,6 +494,7 @@
* 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context.
* 4/2 MIPS_COP_0_USERLOCAL ..36 UserLocal.
* 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register.
+ * 5/1 MIPS_COP_0_PG_GRAIN ..33 PageGrain register
* 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number.
* 7 MIPS_COP_0_HWRENA ..33 rdHWR Enable.
* 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address.
@@ -512,6 +513,8 @@
* 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1.
* 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2.
* 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3.
+ * 16/4 MIPS_COP_0_CONFIG4 ..33 Configuration register 6.
+ * 16/5 MIPS_COP_0_CONFIG5 ..33 Configuration register 7.
* 16/6 MIPS_COP_0_CONFIG6 ..33 Configuration register 6.
* 16/7 MIPS_COP_0_CONFIG7 ..33 Configuration register 7.
* 17 MIPS_COP_0_LLADDR .336 Load Linked Address.
@@ -580,8 +583,35 @@
#define MIPS_COP_0_ERROR_PC _(30)
/* MIPS32/64 */
+#define MIPS_COP_0_CONTEXT _(4)
+#define MIPS_COP_0_CTXCONFIG _(4), 1
+#define MIPS_COP_0_USERLOCAL _(4), 2
+#define MIPS_COP_0_XCTXCONFIG _(4), 3 /* MIPS64 */
+#define MIPS_COP_0_PGGRAIN _(5), 1
+#define MIPS_COP_0_SEGCTL0 _(5), 2
+#define MIPS_COP_0_SEGCTL1 _(5), 3
+#define MIPS_COP_0_SEGCTL2 _(5), 4
+#define MIPS_COP_0_PWBASE _(5), 5
+#define MIPS_COP_0_PWFIELD _(5), 6
+#define MIPS_COP_0_PWSIZE _(5), 7
+#define MIPS_COP_0_PWCTL _(6), 6
#define MIPS_COP_0_HWRENA _(7)
-#define MIPS_COP_0_OSSCRATCH _(22)
+#define MIPS_COP_0_BADINSTR _(8), 1
+#define MIPS_COP_0_BADINSTRP _(8), 2
+#define MIPS_COP_0_INTCTL _(12), 1
+#define MIPS_COP_0_SRSCTL _(12), 2
+#define MIPS_COP_0_SRSMAP _(12), 3
+#define MIPS_COP_0_NESTEDEXC _(13), 5
+#define MIPS_COP_0_NESTED_EPC _(14), 2
+#define MIPS_COP_0_EBASE _(15), 1
+#define MIPS_COP_0_CDMMBASE _(15), 2
+#define MIPS_COP_0_CMGCRBASE _(15), 3
+#define MIPS_COP_0_CONFIG1 _(16), 1
+#define MIPS_COP_0_CONFIG2 _(16), 2
+#define MIPS_COP_0_CONFIG3 _(16), 3
+#define MIPS_COP_0_CONFIG4 _(16), 4
+#define MIPS_COP_0_CONFIG5 _(16), 5
+#define MIPS_COP_0_OSSCRATCH _(22) /* RMI */
#define MIPS_COP_0_DIAG _(22)
#define MIPS_COP_0_DEBUG _(23)
#define MIPS_COP_0_DEPC _(24)
diff -r dc7f8d4bc748 -r 9d0b8c2acd1e sys/arch/mips/mips/locore.S
--- a/sys/arch/mips/mips/locore.S Sun Jun 07 07:19:21 2015 +0000
+++ b/sys/arch/mips/mips/locore.S Sun Jun 07 08:03:10 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.195 2015/06/06 20:55:45 matt Exp $ */
+/* $NetBSD: locore.S,v 1.196 2015/06/07 08:03:10 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -98,7 +98,7 @@
// octeon_cpu_spinup if MP or loop using the wait instruction since
// non-primary CPUs can't do anything useful.
//
- mfc0 a0, MIPS_COP_0_PRID, 1 # EBASE
+ mfc0 a0, MIPS_COP_0_EBASE # EBASE
COP0_SYNC
ext a1, a0, 0, 10 # get CPU number
beqz a1, 2f # normal startup if 0
diff -r dc7f8d4bc748 -r 9d0b8c2acd1e sys/arch/mips/mips/locore_mips3.S
--- a/sys/arch/mips/mips/locore_mips3.S Sun Jun 07 07:19:21 2015 +0000
+++ b/sys/arch/mips/mips/locore_mips3.S Sun Jun 07 08:03:10 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_mips3.S,v 1.107 2015/06/06 21:45:40 matt Exp $ */
+/* $NetBSD: locore_mips3.S,v 1.108 2015/06/07 08:03:10 matt Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@@ -432,7 +432,7 @@
*/
LEAF(mipsNN_cp0_ebase_read)
jr ra
- mfc0 v0, MIPS_COP_0_PRID, 1
+ mfc0 v0, MIPS_COP_0_EBASE
END(mipsNN_cp0_ebase_read)
/*
@@ -443,13 +443,13 @@
and v0, v0, 0x1ff
xor v0, v0, a0
jr ra
- mtc0 v0, MIPS_COP_0_PRID, 1
+ mtc0 v0, MIPS_COP_0_EBASE
END(mipsNN_cp0_ebase_write)
#if (MIPS32R2 + MIPS64R2) > 0
/*
- * void mipsNN_cp0_userlocal_write(void *);
- * Set the value of the CP0 USERLOCAL (TLB_CONTEXT, select 2) register.
+ * void mipsNN_cp0_hwrena_write(void *);
+ * Set the value of the CP0 HWRENA register.
*/
LEAF(mipsNN_cp0_hwrena_write)
jr ra
@@ -462,7 +462,7 @@
*/
LEAF(mipsNN_cp0_userlocal_write)
jr ra
- _MTC0 a0, MIPS_COP_0_TLB_CONTEXT, 2
+ _MTC0 a0, MIPS_COP_0_USERLOCAL
END(mipsNN_cp0_userlocal_write)
#endif /* (MIPS32R2 + MIPS64R2) > 0 */
.set pop
diff -r dc7f8d4bc748 -r 9d0b8c2acd1e sys/arch/mips/mips/locore_octeon.S
--- a/sys/arch/mips/mips/locore_octeon.S Sun Jun 07 07:19:21 2015 +0000
+++ b/sys/arch/mips/mips/locore_octeon.S Sun Jun 07 08:03:10 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_octeon.S,v 1.4 2015/06/06 21:05:16 matt Exp $ */
+/* $NetBSD: locore_octeon.S,v 1.5 2015/06/07 08:03:10 matt Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,7 +27,7 @@
*/
#include <mips/asm.h>
-RCSID("$NetBSD: locore_octeon.S,v 1.4 2015/06/06 21:05:16 matt Exp $")
+RCSID("$NetBSD: locore_octeon.S,v 1.5 2015/06/07 08:03:10 matt Exp $")
#include "cpunode.h" /* for NWDOG */
#include "opt_cputype.h"
@@ -119,12 +119,12 @@
// must has its own exception vector page. The exceptions will be
// modified to refer to that CPU's cpu_info structure.
//
- mfc0 s1, MIPS_COP_0_PRID, 1 # get EBASE
+ mfc0 s1, MIPS_COP_0_EBASE # get EBASE
ext s0, s1, 0, 10 # fetch cpunum (MIPSNNR2)
ins s1, zero, 0, 10 # clear it (MIPSNNR2)
ins s1, s0, 12, 10 # insert cpunum as exception address
ehb
- mtc0 s1, MIPS_COP_0_PRID, 1 # set EBASE
+ mtc0 s1, MIPS_COP_0_EBASE # set EBASE
COP0_SYNC
// we only can deal with 2 cores
@@ -167,7 +167,7 @@
ins k0, zero, V_MIPS_SR_BEV, 1 # clear boot exception vectors
mtc0 k0, MIPS_COP_0_STATUS # write cp0 status
ehb # hazard barrier
- mfc0 k0, MIPS_COP_0_PRID, 1 # get EBASE
+ mfc0 k0, MIPS_COP_0_EBASE # get EBASE
ext k0, k0, 0, 10 # select cpunum
dsll k0, k0, PTR_SCALESHIFT # cpunum -> array index
PTR_LA k1, _C_LABEL(cpuid_infos)
diff -r dc7f8d4bc748 -r 9d0b8c2acd1e sys/arch/mips/mips/mipsX_subr.S
--- a/sys/arch/mips/mips/mipsX_subr.S Sun Jun 07 07:19:21 2015 +0000
+++ b/sys/arch/mips/mips/mipsX_subr.S Sun Jun 07 08:03:10 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.59 2015/06/06 21:48:45 matt Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.60 2015/06/07 08:03:10 matt Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -2655,7 +2655,7 @@
#endif /* !ENABLE_MIPS_16KB_PAGE */
#if (MIPS32R2 + MIPS64R2) > 0
PTR_L v0, L_PRIVATE(a0) # get lwp private
- _MTC0 v0, MIPS_COP_0_TLB_CONTEXT, 4 # make available for rdhwr
+ _MTC0 v0, MIPS_COP_0_USERLOCAL # make available for rdhwr
#endif
jr ra
nop
diff -r dc7f8d4bc748 -r 9d0b8c2acd1e sys/arch/mips/rmi/rmixl_subr.S
--- a/sys/arch/mips/rmi/rmixl_subr.S Sun Jun 07 07:19:21 2015 +0000
+++ b/sys/arch/mips/rmi/rmixl_subr.S Sun Jun 07 08:03:10 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixl_subr.S,v 1.5 2011/04/14 09:25:05 matt Exp $ */
+/* $NetBSD: rmixl_subr.S,v 1.6 2015/06/07 08:03:10 matt Exp $ */
/*-
* Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -37,7 +37,7 @@
#include <mips/asm.h>
#include <mips/cpuregs.h>
-RCSID("$NetBSD: rmixl_subr.S,v 1.5 2011/04/14 09:25:05 matt Exp $");
+RCSID("$NetBSD: rmixl_subr.S,v 1.6 2015/06/07 08:03:10 matt Exp $");
#include "assym.h"
@@ -144,14 +144,14 @@
li t0, 0
#endif
- mtc0 zero, $9, 7 /* disable all in MIPS_COP_0_EIMR */
+ mtc0 zero, RMIXL_COP_0_EIMR /* disable all in MIPS_COP_0_EIMR */
mtc0 t0, MIPS_COP_0_STATUS
/* ensure COP_0_EBASE field 'EBASE' is 0 */
- mfc0 t0, $15, 1 /* MIPS_COP_0_EBASE */
+ mfc0 t0, MIPS_COP_0_EBASE /* MIPS_COP_0_EBASE */
and t0, t0, 0x3ff
- mtc0 t0, $15, 1 /* MIPS_COP_0_EBASE */
+ mtc0 t0, MIPS_COP_0_EBASE /* MIPS_COP_0_EBASE */
/*
* load our stack pointer from trampoline args
@@ -169,7 +169,7 @@
* jump to common mips cpu_trampoline
*/
REG_L a1, 2*SZREG(s0) /* XXX ta_cpuinfo */
- dmtc0 a1, $22, 0 /* MIPS_COP_0_OSSCRATCH */
+ dmtc0 a1, MIPS_COP_0_OSSCRATCH
j cpu_trampoline
nop
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