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[src/trunk]: src/sys/arch/arm/allwinner replace mmc magic bits with symbolic ...



details:   https://anonhg.NetBSD.org/src/rev/1e56c60af8d8
branches:  trunk
changeset: 802259:1e56c60af8d8
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sun Sep 07 15:38:06 2014 +0000

description:
replace mmc magic bits with symbolic names

diffstat:

 sys/arch/arm/allwinner/awin_mmc.c |  60 ++++++++++++-----------
 sys/arch/arm/allwinner/awin_reg.h |  99 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 131 insertions(+), 28 deletions(-)

diffs (truncated from 301 to 300 lines):

diff -r 4d21d2844cbd -r 1e56c60af8d8 sys/arch/arm/allwinner/awin_mmc.c
--- a/sys/arch/arm/allwinner/awin_mmc.c Sun Sep 07 15:28:24 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_mmc.c Sun Sep 07 15:38:06 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_mmc.c,v 1.4 2014/08/24 21:42:06 skrll Exp $ */
+/* $NetBSD: awin_mmc.c,v 1.5 2014/09/07 15:38:06 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2014 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
 #include "locators.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: awin_mmc.c,v 1.4 2014/08/24 21:42:06 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: awin_mmc.c,v 1.5 2014/09/07 15:38:06 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -236,7 +236,7 @@
 #endif
 
        MMC_WRITE(sc, AWIN_MMC_GCTRL,
-           MMC_READ(sc, AWIN_MMC_GCTRL) | __BITS(2,0));
+           MMC_READ(sc, AWIN_MMC_GCTRL) | AWIN_MMC_GCTRL_RESET);
 
        return 0;
 }
@@ -298,11 +298,13 @@
        uint32_t cmd;
        int retry;
 
-       cmd = __BIT(31) | __BIT(21) | __BIT(13);
+       cmd = AWIN_MMC_CMD_START |
+             AWIN_MMC_CMD_UPCLK_ONLY |
+             AWIN_MMC_CMD_WAIT_PRE_OVER;
        MMC_WRITE(sc, AWIN_MMC_CMD, cmd);
        retry = 0xfffff;
        while (--retry > 0) {
-               if (!(MMC_READ(sc, AWIN_MMC_CMD) & __BIT(31)))
+               if (!(MMC_READ(sc, AWIN_MMC_CMD) & AWIN_MMC_CMD_START))
                        break;
                delay(10);
        }
@@ -326,7 +328,7 @@
 #endif
 
        clkcr = MMC_READ(sc, AWIN_MMC_CLKCR);
-       clkcr &= ~__BIT(16);
+       clkcr &= ~AWIN_MMC_CLKCR_CARDCLKON;
        MMC_WRITE(sc, AWIN_MMC_CLKCR, clkcr);
        if (awin_mmc_update_clock(sc) != 0)
                return 1;
@@ -335,13 +337,13 @@
                freq_hz = freq * 1000;
                div = (sc->sc_mod_clk + (freq_hz >> 1)) / freq_hz / 2;
 
-               clkcr &= ~__BITS(15,0);
+               clkcr &= ~AWIN_MMC_CLKCR_DIV;
                clkcr |= div;
                MMC_WRITE(sc, AWIN_MMC_CLKCR, clkcr);
                if (awin_mmc_update_clock(sc) != 0)
                        return 1;
 
-               clkcr |= __BIT(16);
+               clkcr |= AWIN_MMC_CLKCR_CARDCLKON;
                MMC_WRITE(sc, AWIN_MMC_CLKCR, clkcr);
                if (awin_mmc_update_clock(sc) != 0)
                        return 1;
@@ -361,13 +363,13 @@
 
        switch (width) {
        case 1:
-               MMC_WRITE(sc, AWIN_MMC_WIDTH, 0);
+               MMC_WRITE(sc, AWIN_MMC_WIDTH, AWIN_MMC_WIDTH_1);
                break;
        case 4:
-               MMC_WRITE(sc, AWIN_MMC_WIDTH, 1);
+               MMC_WRITE(sc, AWIN_MMC_WIDTH, AWIN_MMC_WIDTH_4);
                break;
        case 8:
-               MMC_WRITE(sc, AWIN_MMC_WIDTH, 2);
+               MMC_WRITE(sc, AWIN_MMC_WIDTH, AWIN_MMC_WIDTH_8);
                break;
        default:
                return 1;
@@ -388,7 +390,8 @@
 awin_mmc_xfer_wait(struct awin_mmc_softc *sc, struct sdmmc_command *cmd)
 {
        int retry = 0xfffff;
-       uint32_t bit = (cmd->c_flags & SCF_CMD_READ) ? __BIT(2) : __BIT(3);
+       uint32_t bit = (cmd->c_flags & SCF_CMD_READ) ?
+           AWIN_MMC_STATUS_FIFO_EMPTY : AWIN_MMC_STATUS_FIFO_FULL;
 
        while (--retry > 0) {
                uint32_t status = MMC_READ(sc, AWIN_MMC_STATUS);
@@ -423,7 +426,7 @@
 awin_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
 {
        struct awin_mmc_softc *sc = sch;
-       uint32_t cmdval = __BIT(31);
+       uint32_t cmdval = AWIN_MMC_CMD_START;
        uint32_t status;
        int retry;
 
@@ -434,20 +437,20 @@
 #endif
 
        if (cmd->c_opcode == 0)
-               cmdval |= __BIT(15);
+               cmdval |= AWIN_MMC_CMD_SEND_INIT_SEQ;
        if (cmd->c_flags & SCF_RSP_PRESENT)
-               cmdval |= __BIT(6);
+               cmdval |= AWIN_MMC_CMD_RSP_EXP;
        if (cmd->c_flags & SCF_RSP_136)
-               cmdval |= __BIT(7);
+               cmdval |= AWIN_MMC_CMD_LONG_RSP;
        if (cmd->c_flags & SCF_RSP_CRC)
-               cmdval |= __BIT(8);
+               cmdval |= AWIN_MMC_CMD_CHECK_RSP_CRC;
 
        if (cmd->c_datalen > 0) {
                unsigned int nblks;
 
-               cmdval |= __BIT(9) | __BIT(13);
+               cmdval |= AWIN_MMC_CMD_DATA_EXP | AWIN_MMC_CMD_WAIT_PRE_OVER;
                if (!ISSET(cmd->c_flags, SCF_CMD_READ)) {
-                       cmdval |= __BIT(10);
+                       cmdval |= AWIN_MMC_CMD_WRITE;
                }
 
                nblks = cmd->c_datalen / cmd->c_blklen;
@@ -455,7 +458,7 @@
                        ++nblks;
 
                if (nblks > 1) {
-                       cmdval |= __BIT(12);
+                       cmdval |= AWIN_MMC_CMD_SEND_AUTO_STOP;
                }
 
                MMC_WRITE(sc, AWIN_MMC_BLKSZ, cmd->c_blklen);
@@ -471,7 +474,7 @@
                MMC_WRITE(sc, AWIN_MMC_CMD, cmdval | cmd->c_opcode);
        } else {
                MMC_WRITE(sc, AWIN_MMC_GCTRL,
-                   MMC_READ(sc, AWIN_MMC_GCTRL) | __BIT(31));
+                   MMC_READ(sc, AWIN_MMC_GCTRL) | AWIN_MMC_GCTRL_ACCESS_BY_AHB);
                MMC_WRITE(sc, AWIN_MMC_CMD, cmdval | cmd->c_opcode);
                cmd->c_resid = cmd->c_datalen;
                cmd->c_buf = cmd->c_data;
@@ -513,14 +516,14 @@
                while (--retry > 0) {
                        uint32_t done;
                        status = MMC_READ(sc, AWIN_MMC_RINT);
-                       if (status & 0xbfc2) {
+                       if (status & AWIN_MMC_INT_ERROR) {
                                retry = 0;
                                break;
                        }
                        if (cmd->c_blklen < cmd->c_datalen)
-                               done = status & __BIT(14);
+                               done = status & AWIN_MMC_INT_AUTO_CMD_DONE;
                        else
-                               done = status & __BIT(3);
+                               done = status & AWIN_MMC_INT_DATA_OVER;
                        if (done)
                                break;
                        delay(10);
@@ -539,7 +542,7 @@
                retry = 0xfffff;
                while (--retry > 0) {
                        status = MMC_READ(sc, AWIN_MMC_STATUS);
-                       if (status & __BIT(9))
+                       if (status & AWIN_MMC_STATUS_CARD_DATA_BUSY)
                                break;
                }
                if (retry == 0) {
@@ -576,11 +579,12 @@
        cmd->c_flags |= SCF_ITSDONE;
 
        if (cmd->c_error) {
-               MMC_WRITE(sc, AWIN_MMC_GCTRL, __BITS(2,0));
+               MMC_WRITE(sc, AWIN_MMC_GCTRL, AWIN_MMC_GCTRL_RESET);
                awin_mmc_update_clock(sc);
        }
-       MMC_WRITE(sc, AWIN_MMC_RINT, __BITS(31,0));
-       MMC_WRITE(sc, AWIN_MMC_GCTRL, MMC_READ(sc, AWIN_MMC_GCTRL) | __BIT(1));
+       MMC_WRITE(sc, AWIN_MMC_RINT, 0xffffffff);
+       MMC_WRITE(sc, AWIN_MMC_GCTRL,
+           MMC_READ(sc, AWIN_MMC_GCTRL) | AWIN_MMC_GCTRL_FIFORESET);
 }
 
 static void
diff -r 4d21d2844cbd -r 1e56c60af8d8 sys/arch/arm/allwinner/awin_reg.h
--- a/sys/arch/arm/allwinner/awin_reg.h Sun Sep 07 15:28:24 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Sun Sep 07 15:38:06 2014 +0000
@@ -620,6 +620,105 @@
 #define AWIN_MMC_CBDA                  0x0094
 #define AWIN_MMC_FIFO                  0x0100
 
+#define AWIN_MMC_GCTRL_ACCESS_BY_AHB   __BIT(31)
+#define AWIN_MMC_GCTRL_WAIT_MEM_ACCESS_DONE __BIT(30)
+#define AWIN_MMC_GCTRL_DDR_MODE                __BIT(10)
+#define AWIN_MMC_GCTRL_DEBOUNCEEN      __BIT(8)
+#define AWIN_MMC_GCTRL_DMAEN           __BIT(5)
+#define AWIN_MMC_GCTRL_INTEN           __BIT(4)
+#define AWIN_MMC_GCTRL_DMARESET                __BIT(2)
+#define AWIN_MMC_GCTRL_FIFORESET       __BIT(1)
+#define AWIN_MMC_GCTRL_SOFTRESET       __BIT(0)
+#define AWIN_MMC_GCTRL_RESET \
+       (AWIN_MMC_GCTRL_SOFTRESET | AWIN_MMC_GCTRL_FIFORESET | \
+        AWIN_MMC_GCTRL_DMARESET)
+
+#define AWIN_MMC_CLKCR_LOWPOWERON      __BIT(17)
+#define AWIN_MMC_CLKCR_CARDCLKON       __BIT(16)
+#define AWIN_MMC_CLKCR_DIV             __BITS(15,0)
+
+#define AWIN_MMC_WIDTH_1               0
+#define AWIN_MMC_WIDTH_4               1
+#define AWIN_MMC_WIDTH_8               2
+
+#define AWIN_MMC_CMD_START             __BIT(31)
+#define AWIN_MMC_CMD_USE_HOLD_REG      __BIT(29)
+#define AWIN_MMC_CMD_VOL_SWITCH                __BIT(28)
+#define AWIN_MMC_CMD_BOOT_ABORT                __BIT(27)
+#define AWIN_MMC_CMD_BOOT_ACK_EXP      __BIT(26)
+#define AWIN_MMC_CMD_ALT_BOOT_OPT      __BIT(25)
+#define AWIN_MMC_CMD_ENBOOT            __BIT(24)
+#define AWIN_MMC_CMD_CCS_EXP           __BIT(23)
+#define AWIN_MMC_CMD_RD_CEATA_DEV      __BIT(22)
+#define AWIN_MMC_CMD_UPCLK_ONLY                __BIT(21)
+#define AWIN_MMC_CMD_SEND_INIT_SEQ     __BIT(15)
+#define AWIN_MMC_CMD_STOP_ABORT_CMD    __BIT(14)
+#define AWIN_MMC_CMD_WAIT_PRE_OVER     __BIT(13)
+#define AWIN_MMC_CMD_SEND_AUTO_STOP    __BIT(12)
+#define AWIN_MMC_CMD_SEQMOD            __BIT(11)
+#define AWIN_MMC_CMD_WRITE             __BIT(10)
+#define AWIN_MMC_CMD_DATA_EXP          __BIT(9)
+#define AWIN_MMC_CMD_CHECK_RSP_CRC     __BIT(8)
+#define AWIN_MMC_CMD_LONG_RSP          __BIT(7)
+#define AWIN_MMC_CMD_RSP_EXP           __BIT(6)
+
+#define AWIN_MMC_INT_CARD_REMOVE       __BIT(31)
+#define AWIN_MMC_INT_CARD_INSERT       __BIT(30)
+#define AWIN_MMC_INT_SDIO_INT          __BIT(16)
+#define AWIN_MMC_INT_END_BIT_ERR       __BIT(15)
+#define AWIN_MMC_INT_AUTO_CMD_DONE     __BIT(14)
+#define AWIN_MMC_INT_START_BIT_ERR     __BIT(13)
+#define AWIN_MMC_INT_HW_LOCKED         __BIT(12)
+#define AWIN_MMC_INT_FIFO_RUN_ERR      __BIT(11)
+#define AWIN_MMC_INT_VOL_CHG_DONE      __BIT(10)
+#define AWIN_MMC_INT_DATA_STARVE       __BIT(10)
+#define AWIN_MMC_INT_BOOT_START                __BIT(9)
+#define AWIN_MMC_INT_DATA_TIMEOUT      __BIT(9)
+#define AWIN_MMC_INT_ACK_RCV           __BIT(8)
+#define AWIN_MMC_INT_RESP_TIMEOUT      __BIT(8)
+#define AWIN_MMC_INT_DATA_CRC_ERR      __BIT(7)
+#define AWIN_MMC_INT_RESP_CRC_ERR      __BIT(6)
+#define AWIN_MMC_INT_RX_DATA_REQ       __BIT(5)
+#define AWIN_MMC_INT_TX_DATA_REQ       __BIT(4)
+#define AWIN_MMC_INT_DATA_OVER         __BIT(3)
+#define AWIN_MMC_INT_CMD_DONE          __BIT(2)
+#define AWIN_MMC_INT_RESP_ERR          __BIT(1)
+#define AWIN_MMC_INT_ERROR \
+       (AWIN_MMC_INT_RESP_ERR | AWIN_MMC_INT_RESP_CRC_ERR | \
+        AWIN_MMC_INT_DATA_CRC_ERR | AWIN_MMC_INT_RESP_TIMEOUT | \
+        AWIN_MMC_INT_FIFO_RUN_ERR | AWIN_MMC_INT_HW_LOCKED | \
+        AWIN_MMC_INT_START_BIT_ERR  | AWIN_MMC_INT_END_BIT_ERR)
+
+#define AWIN_MMC_STATUS_DMAREQ         __BIT(31)
+#define AWIN_MMC_STATUS_DATA_FSM_BUSY  __BIT(10)
+#define AWIN_MMC_STATUS_CARD_DATA_BUSY __BIT(9)
+#define AWIN_MMC_STATUS_CARD_PRESENT   __BIT(8)
+#define AWIN_MMC_STATUS_FIFO_FULL      __BIT(3)
+#define AWIN_MMC_STATUS_FIFO_EMPTY     __BIT(2)
+#define AWIN_MMC_STATUS_TXWL_FLAG      __BIT(1)
+#define AWIN_MMC_STATUS_RXWL_FLAG      __BIT(0)
+
+#define AWIN_MMC_FUNCSEL_CEATA_DEV_INTEN __BIT(10)
+#define AWIN_MMC_FUNCSEL_SEND_AUTO_STOP_CCSD __BIT(9)
+#define AWIN_MMC_FUNCSEL_SEND_CCSD     __BIT(8)
+#define AWIN_MMC_FUNCSEL_ABT_RD_DATA   __BIT(2)
+#define AWIN_MMC_FUNCSEL_SDIO_RD_WAIT  __BIT(1)
+#define AWIN_MMC_FUNCSEL_SEND_IRQ_RSP  __BIT(0)
+
+#define AWIN_MMC_DMAC_REFETCH_DES      __BIT(31)
+#define AWIN_MMC_DMAC_IDMA_ON          __BIT(7)
+#define AWIN_MMC_DMAC_FIX_BURST                __BIT(1)
+#define AWIN_MMC_DMAC_SOFTRESET                __BIT(0)
+
+#define AWIN_MMC_IDST_HOST_ABT         __BIT(10)
+#define AWIN_MMC_IDST_ABNORMAL_INT_SUM __BIT(9)
+#define AWIN_MMC_IDST_NORMAL_INT_SUM   __BIT(8)
+#define AWIN_MMC_IDST_CARD_ERR_SUM     __BIT(5)
+#define AWIN_MMC_IDST_DES_INVALID      __BIT(4)
+#define AWIN_MMC_IDST_FATAL_BUS_ERR    __BIT(2)
+#define AWIN_MMC_IDST_RECEIVE_INT      __BIT(1)
+#define AWIN_MMC_IDST_TRANSMIT_INT     __BIT(0)
+
 #define AWIN_CPUCFG_CPU0_RST_CTRL_REG  0x0040
 #define AWIN_CPUCFG_CPU0_CTRL_REG      0x0044



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