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[src/trunk]: src/sys/dev/pci - Add some register definitions (subclass, power...
details: https://anonhg.NetBSD.org/src/rev/bd8104b5bafa
branches: trunk
changeset: 796181:bd8104b5bafa
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Fri May 23 18:32:13 2014 +0000
description:
- Add some register definitions (subclass, power management, etc.)
- Print some information (subclass, power management)
- Use macro.
diffstat:
sys/dev/pci/pci_subr.c | 43 ++++++++++++++++++++++-------------
sys/dev/pci/pcireg.h | 59 ++++++++++++++++++++++++++++++++++++++++++-------
2 files changed, 77 insertions(+), 25 deletions(-)
diffs (217 lines):
diff -r deefd7a02a49 -r bd8104b5bafa sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c Fri May 23 17:54:08 2014 +0000
+++ b/sys/dev/pci/pci_subr.c Fri May 23 18:32:13 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.113 2014/05/23 17:54:08 msaitoh Exp $ */
+/* $NetBSD: pci_subr.c,v 1.114 2014/05/23 18:32:13 msaitoh Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.113 2014/05/23 17:54:08 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.114 2014/05/23 18:32:13 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -208,6 +208,7 @@
{ "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, },
{ "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, },
{ "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, },
+ { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -225,6 +226,7 @@
static const struct pci_class pci_subclass_i2o[] = {
{ "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, },
+ { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -233,6 +235,7 @@
{ "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, },
{ "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, },
{ "data", PCI_SUBCLASS_SATCOM_DATA, NULL, },
+ { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -1402,30 +1405,38 @@
pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff)
{
uint16_t caps, pmcsr;
+ pcireg_t reg;
- caps = regs[o2i(capoff)] >> 16;
- pmcsr = regs[o2i(capoff + 0x04)] & 0xffff;
+ caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT;
+ reg = regs[o2i(capoff + PCI_PMCSR)];
+ pmcsr = reg & 0xffff;
printf("\n PCI Power Management Capabilities Register\n");
printf(" Capabilities register: 0x%04x\n", caps);
printf(" Version: %s\n",
- pci_conf_print_pcipm_cap_pmrev(caps & 0x3));
+ pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK));
onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK);
- onoff("Device specific initialization", caps, 0x20);
+ onoff("Device specific initialization", caps, PCI_PMCR_DSI);
printf(" 3.3V auxiliary current: %s\n",
pci_conf_print_pcipm_cap_aux(caps));
- onoff("D1 power management state support", (caps >> 9), 1);
- onoff("D2 power management state support", (caps >> 10), 1);
+ onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP);
+ onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP);
printf(" PME# support: 0x%02x\n", caps >> 11);
printf(" Control/status register: 0x%04x\n", pmcsr);
- printf(" Power state: D%d\n", pmcsr & 3);
+ printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK);
onoff("PCI Express reserved", (pmcsr >> 2), 1);
onoff("No soft reset", (pmcsr >> 3), 1);
- printf(" PME# assertion %sabled\n",
- (pmcsr >> 8) & 1 ? "en" : "dis");
- printf(" PME# status: %s\n", (pmcsr >> 15) ? "on" : "off");
+ printf(" PME# assertion: %sabled\n",
+ (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis");
+ onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS);
+ printf(" Bridge Support Extensions register: 0x%02x\n",
+ (reg >> 16) & 0xff);
+ onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT);
+ onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN);
+ printf(" Data register: 0x%02x\n", (reg >> 24) & 0xff);
+
}
static void
@@ -1632,13 +1643,13 @@
rval = regs[o2i(PCI_BRIDGE_BUS_REG)];
printf(" Primary bus number: 0x%02x\n",
- (rval >> 0) & 0xff);
+ PCI_BRIDGE_BUS_PRIMARY(rval));
printf(" Secondary bus number: 0x%02x\n",
- (rval >> 8) & 0xff);
+ PCI_BRIDGE_BUS_SECONDARY(rval));
printf(" Subordinate bus number: 0x%02x\n",
- (rval >> 16) & 0xff);
+ PCI_BRIDGE_BUS_SUBORDINATE(rval));
printf(" Secondary bus latency timer: 0x%02x\n",
- (rval >> 24) & 0xff);
+ PCI_BRIDGE_BUS_SEC_LATTIMER(rval));
rval = regs[o2i(PCI_BRIDGE_STATIO_REG)];
pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16)));
diff -r deefd7a02a49 -r bd8104b5bafa sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h Fri May 23 17:54:08 2014 +0000
+++ b/sys/dev/pci/pcireg.h Fri May 23 18:32:13 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.88 2014/05/23 17:54:08 msaitoh Exp $ */
+/* $NetBSD: pcireg.h,v 1.89 2014/05/23 18:32:13 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -274,6 +274,7 @@
#define PCI_SUBCLASS_SERIALBUS_IPMI 0x07
#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08
#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09
+#define PCI_SUBCLASS_SERIALBUS_MISC 0x80
/* 0x0d wireless subclasses */
#define PCI_SUBCLASS_WIRELESS_IRDA 0x00
@@ -287,6 +288,7 @@
/* 0x0e I2O (Intelligent I/O) subclasses */
#define PCI_SUBCLASS_I2O_STANDARD 0x00
+#define PCI_SUBCLASS_I2O_MISC 0x80
/* 0x0f satellite communication subclasses */
/* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */
@@ -294,6 +296,7 @@
#define PCI_SUBCLASS_SATCOM_AUDIO 0x02
#define PCI_SUBCLASS_SATCOM_VOICE 0x03
#define PCI_SUBCLASS_SATCOM_DATA 0x04
+#define PCI_SUBCLASS_SATCOM_MISC 0x80
/* 0x10 encryption/decryption subclasses */
#define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00
@@ -479,18 +482,45 @@
/* Power Management Capability Register */
#define PCI_PMCR_SHIFT 16
#define PCI_PMCR 0x02
+#define PCI_PMCR_VERSION_MASK 0x0007
+#define PCI_PMCR_VERSION_10 0x0001
+#define PCI_PMCR_VERSION_11 0x0002
+#define PCI_PMCR_VERSION_12 0x0003
#define PCI_PMCR_PME_CLOCK 0x0008
+#define PCI_PMCR_DSI 0x0020
+#define PCI_PMCR_AUXCUR_MASK 0x01c0
+#define PCI_PMCR_AUXCUR_0 0x0000
+#define PCI_PMCR_AUXCUR_55 0x0040
+#define PCI_PMCR_AUXCUR_100 0x0080
+#define PCI_PMCR_AUXCUR_160 0x00c0
+#define PCI_PMCR_AUXCUR_220 0x0100
+#define PCI_PMCR_AUXCUR_270 0x0140
+#define PCI_PMCR_AUXCUR_320 0x0180
+#define PCI_PMCR_AUXCUR_375 0x01c0
#define PCI_PMCR_D1SUPP 0x0200
#define PCI_PMCR_D2SUPP 0x0400
-/* Power Management Control Status Register */
+#define PCI_PMCR_PME_D0 0x0800
+#define PCI_PMCR_PME_D1 0x1000
+#define PCI_PMCR_PME_D2 0x2000
+#define PCI_PMCR_PME_D3HOT 0x4000
+#define PCI_PMCR_PME_D3COLD 0x8000
+/*
+ * Power Management Control Status Register, Bridge Support Extensions Register
+ * and Data Register.
+ */
#define PCI_PMCSR 0x04
-#define PCI_PMCSR_PME_EN 0x100
-#define PCI_PMCSR_STATE_MASK 0x03
-#define PCI_PMCSR_STATE_D0 0x00
-#define PCI_PMCSR_STATE_D1 0x01
-#define PCI_PMCSR_STATE_D2 0x02
-#define PCI_PMCSR_STATE_D3 0x03
-#define PCI_PMCSR_PME_STS 0x8000
+#define PCI_PMCSR_STATE_MASK 0x00000003
+#define PCI_PMCSR_STATE_D0 0x00000000
+#define PCI_PMCSR_STATE_D1 0x00000001
+#define PCI_PMCSR_STATE_D2 0x00000002
+#define PCI_PMCSR_STATE_D3 0x00000003
+#define PCI_PMCSR_PME_EN 0x00000100
+#define PCI_PMCSR_DATASEL_MASK 0x00001e00
+#define PCI_PMCSR_DATASCL_MASK 0x00006000
+#define PCI_PMCSR_PME_STS 0x00008000
+#define PCI_PMCSR_B2B3_SUPPORT 0x00400000
+#define PCI_PMCSR_BPCC_EN 0x00800000
+
/*
* Capability ID: 0x02
@@ -935,9 +965,20 @@
/* Header Type 1 (Bridge) configuration registers */
#define PCI_BRIDGE_BUS_REG 0x18
+#define PCI_BRIDGE_BUS_EACH_MASK 0xff
#define PCI_BRIDGE_BUS_PRIMARY_SHIFT 0
#define PCI_BRIDGE_BUS_SECONDARY_SHIFT 8
#define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT 16
+#define PCI_BRIDGE_BUS_SEC_LATTIMER_SHIFT 24
+#define PCI_BRIDGE_BUS_PRIMARY(reg) \
+ (((reg) >> PCI_BRIDGE_BUS_PRIMARY_SHIFT) & PCI_BRIDGE_BUS_EACH_MASK)
+#define PCI_BRIDGE_BUS_SECONDARY(reg) \
+ (((reg) >> PCI_BRIDGE_BUS_SECONDARY_SHIFT) & PCI_BRIDGE_BUS_EACH_MASK)
+#define PCI_BRIDGE_BUS_SUBORDINATE(reg) \
+ (((reg) >> PCI_BRIDGE_BUS_SUBORDINATE_SHIFT) &PCI_BRIDGE_BUS_EACH_MASK)
+#define PCI_BRIDGE_BUS_SEC_LATTIMER(reg) \
+ (((reg) >> PCI_BRIDGE_BUS_SEC_LATTIMER_SHIFT)&PCI_BRIDGE_BUS_EACH_MASK)
+
#define PCI_BRIDGE_STATIO_REG 0x1C
#define PCI_BRIDGE_STATIO_IOBASE_SHIFT 0
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