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[src/trunk]: src/external/gpl3 Add RISC-V support.
details: https://anonhg.NetBSD.org/src/rev/cf48a62b25d4
branches: trunk
changeset: 802528:cf48a62b25d4
user: matt <matt%NetBSD.org@localhost>
date: Fri Sep 19 17:19:52 2014 +0000
description:
Add RISC-V support.
diffstat:
external/gpl3/binutils/dist/bfd/archures.c | 5 +
external/gpl3/binutils/dist/bfd/bfd-in2.h | 40 +
external/gpl3/binutils/dist/bfd/config.bfd | 9 +
external/gpl3/binutils/dist/bfd/configure | 2 +
external/gpl3/binutils/dist/bfd/configure.in | 4 +
external/gpl3/binutils/dist/bfd/cpu-riscv.c | 80 +
external/gpl3/binutils/dist/bfd/elf-bfd.h | 1 +
external/gpl3/binutils/dist/bfd/elf32-riscv.c | 193 +
external/gpl3/binutils/dist/bfd/elf64-riscv.c | 218 +
external/gpl3/binutils/dist/bfd/elfxx-riscv.c | 5444 ++++++
external/gpl3/binutils/dist/bfd/elfxx-riscv.h | 109 +
external/gpl3/binutils/dist/bfd/libbfd.h | 35 +
external/gpl3/binutils/dist/bfd/targets.c | 15 +-
external/gpl3/binutils/dist/binutils/readelf.c | 6 +
external/gpl3/binutils/dist/config.sub | 8 +
external/gpl3/binutils/dist/gas/Makefile.am | 2 +
external/gpl3/binutils/dist/gas/Makefile.in | 17 +
external/gpl3/binutils/dist/gas/config/tc-riscv.c | 3245 +++
external/gpl3/binutils/dist/gas/config/tc-riscv.h | 129 +
external/gpl3/binutils/dist/gas/configure.tgt | 9 +-
external/gpl3/binutils/dist/include/dis-asm.h | 1 +
external/gpl3/binutils/dist/include/elf/common.h | 1 +
external/gpl3/binutils/dist/include/elf/riscv.h | 174 +
external/gpl3/binutils/dist/include/opcode/riscv-opc.h | 1216 +
external/gpl3/binutils/dist/include/opcode/riscv.h | 317 +
external/gpl3/binutils/dist/ld/Makefile.am | 11 +
external/gpl3/binutils/dist/ld/Makefile.in | 13 +
external/gpl3/binutils/dist/ld/configure.tgt | 6 +
external/gpl3/binutils/dist/ld/emulparams/elf32lriscv-defs.sh | 59 +
external/gpl3/binutils/dist/ld/emulparams/elf32lriscv.sh | 9 +
external/gpl3/binutils/dist/ld/emulparams/elf64lriscv-defs.sh | 2 +
external/gpl3/binutils/dist/ld/emulparams/elf64lriscv.sh | 8 +
external/gpl3/binutils/dist/ld/emultempl/riscvelf.em | 63 +
external/gpl3/binutils/dist/ld/ldgram.c | 8138 ++++-----
external/gpl3/binutils/dist/ld/ldgram.h | 447 +-
external/gpl3/binutils/dist/opcodes/configure | 1 +
external/gpl3/binutils/dist/opcodes/configure.in | 1 +
external/gpl3/binutils/dist/opcodes/disassemble.c | 6 +
external/gpl3/binutils/dist/opcodes/riscv-dis.c | 761 +
external/gpl3/binutils/dist/opcodes/riscv-opc.c | 683 +
external/gpl3/gcc/dist/config.sub | 8 +
external/gpl3/gcc/dist/gcc/common/config/riscv/riscv-common.c | 59 +
external/gpl3/gcc/dist/gcc/config.gcc | 53 +
external/gpl3/gcc/dist/gcc/config/riscv/constraints.md | 95 +
external/gpl3/gcc/dist/gcc/config/riscv/crti.asm | 42 +
external/gpl3/gcc/dist/gcc/config/riscv/crtn.asm | 38 +
external/gpl3/gcc/dist/gcc/config/riscv/div.S | 121 +
external/gpl3/gcc/dist/gcc/config/riscv/elf.h | 31 +
external/gpl3/gcc/dist/gcc/config/riscv/generic.md | 98 +
external/gpl3/gcc/dist/gcc/config/riscv/linux-unwind.h | 50 +
external/gpl3/gcc/dist/gcc/config/riscv/linux.h | 60 +
external/gpl3/gcc/dist/gcc/config/riscv/linux64.h | 44 +
external/gpl3/gcc/dist/gcc/config/riscv/netbsd.h | 111 +
external/gpl3/gcc/dist/gcc/config/riscv/opcode-riscv.h | 150 +
external/gpl3/gcc/dist/gcc/config/riscv/peephole.md | 122 +
external/gpl3/gcc/dist/gcc/config/riscv/predicates.md | 182 +
external/gpl3/gcc/dist/gcc/config/riscv/riscv-fp.c | 178 +
external/gpl3/gcc/dist/gcc/config/riscv/riscv-ftypes.def | 39 +
external/gpl3/gcc/dist/gcc/config/riscv/riscv-modes.def | 26 +
external/gpl3/gcc/dist/gcc/config/riscv/riscv-opc.h | 1216 +
external/gpl3/gcc/dist/gcc/config/riscv/riscv-protos.h | 90 +
external/gpl3/gcc/dist/gcc/config/riscv/riscv.c | 4687 +++++
external/gpl3/gcc/dist/gcc/config/riscv/riscv.h | 1198 +
external/gpl3/gcc/dist/gcc/config/riscv/riscv.md | 2425 ++
external/gpl3/gcc/dist/gcc/config/riscv/riscv.opt | 63 +
external/gpl3/gcc/dist/gcc/config/riscv/sync.md | 197 +
external/gpl3/gcc/dist/gcc/config/riscv/t-elf | 5 +
external/gpl3/gcc/dist/gcc/config/riscv/t-linux64 | 6 +
external/gpl3/gcc/dist/gcc/config/riscv/t-netbsd64 | 21 +
external/gpl3/gcc/dist/gcc/configure | 19 +
external/gpl3/gcc/dist/gcc/configure.ac | 19 +
external/gpl3/gcc/dist/gcc/tree-ssa-ccp.c | 3 +-
external/gpl3/gcc/dist/libgcc/config.host | 14 +
external/gpl3/gcc/dist/libgcc/config/riscv/crti.S | 1 +
external/gpl3/gcc/dist/libgcc/config/riscv/crtn.S | 1 +
external/gpl3/gcc/dist/libgcc/config/riscv/riscv-fp.c | 178 +
external/gpl3/gcc/dist/libgcc/config/riscv/t-dpbit | 4 +
external/gpl3/gcc/dist/libgcc/config/riscv/t-elf | 2 +
external/gpl3/gcc/dist/libgcc/config/riscv/t-fpbit | 5 +
external/gpl3/gcc/dist/libgcc/config/riscv/t-linux | 1 +
external/gpl3/gcc/dist/libgcc/config/riscv/t-tpbit | 10 +
81 files changed, 28280 insertions(+), 4880 deletions(-)
diffs (truncated from 33958 to 300 lines):
diff -r 80f923f79fb2 -r cf48a62b25d4 external/gpl3/binutils/dist/bfd/archures.c
--- a/external/gpl3/binutils/dist/bfd/archures.c Fri Sep 19 16:06:16 2014 +0000
+++ b/external/gpl3/binutils/dist/bfd/archures.c Fri Sep 19 17:19:52 2014 +0000
@@ -245,6 +245,9 @@
.#define bfd_mach_ppc_e6500 5007
.#define bfd_mach_ppc_titan 83
.#define bfd_mach_ppc_vle 84
+. bfd_arch_riscv, {* RISC-V *}
+.#define bfd_mach_riscv32 132
+.#define bfd_mach_riscv64 164
. bfd_arch_rs6000, {* IBM RS/6000 *}
.#define bfd_mach_rs6k 6000
.#define bfd_mach_rs6k_rs1 6001
@@ -562,6 +565,7 @@
extern const bfd_arch_info_type bfd_plugin_arch;
extern const bfd_arch_info_type bfd_powerpc_archs[];
#define bfd_powerpc_arch bfd_powerpc_archs[0]
+extern const bfd_arch_info_type bfd_riscv_arch;
extern const bfd_arch_info_type bfd_rs6000_arch;
extern const bfd_arch_info_type bfd_rl78_arch;
extern const bfd_arch_info_type bfd_rx_arch;
@@ -645,6 +649,7 @@
&bfd_or1k_arch,
&bfd_pdp11_arch,
&bfd_powerpc_arch,
+ &bfd_riscv_arch,
&bfd_rs6000_arch,
&bfd_rl78_arch,
&bfd_rx_arch,
diff -r 80f923f79fb2 -r cf48a62b25d4 external/gpl3/binutils/dist/bfd/bfd-in2.h
--- a/external/gpl3/binutils/dist/bfd/bfd-in2.h Fri Sep 19 16:06:16 2014 +0000
+++ b/external/gpl3/binutils/dist/bfd/bfd-in2.h Fri Sep 19 17:19:52 2014 +0000
@@ -1976,6 +1976,9 @@
#define bfd_mach_ppc_e6500 5007
#define bfd_mach_ppc_titan 83
#define bfd_mach_ppc_vle 84
+ bfd_arch_riscv, /* RISC-V */
+#define bfd_mach_riscv32 132
+#define bfd_mach_riscv64 164
bfd_arch_rs6000, /* IBM RS/6000 */
#define bfd_mach_rs6k 6000
#define bfd_mach_rs6k_rs1 6001
@@ -4831,6 +4834,43 @@
BFD_RELOC_OR1K_TLS_DTPOFF,
BFD_RELOC_OR1K_TLS_DTPMOD,
+/* RISC-V relocations. */
+ BFD_RELOC_RISCV_ADD32,
+ BFD_RELOC_RISCV_ADD64,
+ BFD_RELOC_RISCV_SUB32,
+ BFD_RELOC_RISCV_SUB64,
+ BFD_RELOC_RISCV_HI20,
+ BFD_RELOC_RISCV_LO12_I,
+ BFD_RELOC_RISCV_LO12_S,
+ BFD_RELOC_RISCV_PCREL_LO12_I,
+ BFD_RELOC_RISCV_PCREL_LO12_S,
+ BFD_RELOC_RISCV_CALL,
+ BFD_RELOC_RISCV_CALL_PLT,
+ BFD_RELOC_RISCV_PCREL_HI20,
+ BFD_RELOC_RISCV_JMP,
+ BFD_RELOC_RISCV_GOT_HI20,
+ BFD_RELOC_RISCV_GOT_LO12,
+ BFD_RELOC_RISCV_TLS_DTPMOD32,
+ BFD_RELOC_RISCV_TLS_DTPREL32,
+ BFD_RELOC_RISCV_TLS_DTPMOD64,
+ BFD_RELOC_RISCV_TLS_DTPREL64,
+ BFD_RELOC_RISCV_TLS_TPREL32,
+ BFD_RELOC_RISCV_TLS_TPREL64,
+ BFD_RELOC_RISCV_TPREL_HI20,
+ BFD_RELOC_RISCV_TPREL_ADD,
+ BFD_RELOC_RISCV_TPREL_LO12_S,
+ BFD_RELOC_RISCV_TPREL_LO12_I,
+ BFD_RELOC_RISCV_TLS_IE_HI20,
+ BFD_RELOC_RISCV_TLS_IE_LO12,
+ BFD_RELOC_RISCV_TLS_IE_ADD,
+ BFD_RELOC_RISCV_TLS_IE_LO12_S,
+ BFD_RELOC_RISCV_TLS_IE_LO12_I,
+ BFD_RELOC_RISCV_TLS_GOT_HI20,
+ BFD_RELOC_RISCV_TLS_GOT_LO12,
+ BFD_RELOC_RISCV_TLS_GD_HI20,
+ BFD_RELOC_RISCV_TLS_GD_LO12,
+ BFD_RELOC_RISCV_TLS_PCREL_LO12,
+
/* H8 elf Relocations. */
BFD_RELOC_H8_DIR16A8,
BFD_RELOC_H8_DIR16R8,
diff -r 80f923f79fb2 -r cf48a62b25d4 external/gpl3/binutils/dist/bfd/config.bfd
--- a/external/gpl3/binutils/dist/bfd/config.bfd Fri Sep 19 16:06:16 2014 +0000
+++ b/external/gpl3/binutils/dist/bfd/config.bfd Fri Sep 19 17:19:52 2014 +0000
@@ -97,6 +97,7 @@
pdp11*) targ_archs=bfd_pdp11_arch ;;
pj*) targ_archs="bfd_pj_arch bfd_i386_arch";;
powerpc*) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
+riscv*) targ_archs=bfd_riscv_arch ;;
rs6000) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
s390*) targ_archs=bfd_s390_arch ;;
sh*) targ_archs=bfd_sh_arch ;;
@@ -1272,6 +1273,14 @@
targ_defvec=bfd_elf32_rl78_vec
;;
+#ifdef BFD64
+ riscv*-*-*)
+ targ_defvec=bfd_elf64_riscv_vec
+ targ_selvecs="bfd_elf32_riscv_vec bfd_elf64_riscv_vec"
+ want64=true
+ ;;
+#endif
+
rx-*-elf)
targ_defvec=bfd_elf32_rx_le_vec
targ_selvecs="bfd_elf32_rx_be_vec bfd_elf32_rx_le_vec bfd_elf32_rx_be_ns_vec"
diff -r 80f923f79fb2 -r cf48a62b25d4 external/gpl3/binutils/dist/bfd/configure
--- a/external/gpl3/binutils/dist/bfd/configure Fri Sep 19 16:06:16 2014 +0000
+++ b/external/gpl3/binutils/dist/bfd/configure Fri Sep 19 17:19:52 2014 +0000
@@ -15286,6 +15286,7 @@
bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
bfd_elf32_powerpc_freebsd_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
bfd_elf32_powerpc_vxworks_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
+ bfd_elf32_riscv_vec) tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf" ;;
bfd_elf32_rl78_vec) tb="$tb elf32-rl78.lo $elf" ;;
bfd_elf32_rx_le_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;;
bfd_elf32_rx_be_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;;
@@ -15356,6 +15357,7 @@
bfd_elf64_powerpc_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_powerpcle_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf" target_size=64 ;;
bfd_elf64_powerpc_freebsd_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf" target_size=64 ;;
+ bfd_elf64_riscv_vec) tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;;
bfd_elf64_s390_vec) tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_sh64_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;;
bfd_elf64_sh64l_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;;
diff -r 80f923f79fb2 -r cf48a62b25d4 external/gpl3/binutils/dist/bfd/configure.in
--- a/external/gpl3/binutils/dist/bfd/configure.in Fri Sep 19 16:06:16 2014 +0000
+++ b/external/gpl3/binutils/dist/bfd/configure.in Fri Sep 19 17:19:52 2014 +0000
@@ -773,6 +773,7 @@
tb="$tb elfn32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf32_openrisc_vec) tb="$tb elf32-openrisc.lo elf32.lo $elf" ;;
bfd_elf32_or1k_big_vec) tb="$tb elf32-or1k.lo elf32.lo $elf" ;;
+ bfd_elf32_riscv_vec) tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;;
bfd_elf32_pj_vec) tb="$tb elf32-pj.lo elf32.lo $elf";;
bfd_elf32_pjl_vec) tb="$tb elf32-pj.lo elf32.lo $elf";;
bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
@@ -836,6 +837,7 @@
bfd_elf64_bigaarch64_vec) tb="$tb elf64-aarch64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_big_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_bigmips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
+ bfd_elf32_m32c_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;;
bfd_elf64_hppa_linux_vec) tb="$tb elf64-hppa.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_hppa_vec) tb="$tb elf64-hppa.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_ia64_big_vec) tb="$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $elf"; target_size=64 ;;
@@ -845,10 +847,12 @@
bfd_elf64_littleaarch64_vec)tb="$tb elf64-aarch64.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_little_generic_vec) tb="$tb elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_littlemips_vec) tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
+ bfd_elf32_m32c_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;;
bfd_elf64_mmix_vec) tb="$tb elf64-mmix.lo elf64.lo $elf" target_size=64 ;;
bfd_elf64_powerpc_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_powerpcle_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf" target_size=64 ;;
bfd_elf64_powerpc_freebsd_vec) tb="$tb elf64-ppc.lo elf64-gen.lo elf64.lo $elf" target_size=64 ;;
+ bfd_elf64_riscv_vec) tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;;
bfd_elf64_s390_vec) tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_sh64_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;;
bfd_elf64_sh64l_vec) tb="$tb elf64-sh64.lo elf64.lo $elf" target_size=64 ;;
diff -r 80f923f79fb2 -r cf48a62b25d4 external/gpl3/binutils/dist/bfd/cpu-riscv.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/external/gpl3/binutils/dist/bfd/cpu-riscv.c Fri Sep 19 17:19:52 2014 +0000
@@ -0,0 +1,80 @@
+/* BFD backend for RISC-V
+ Copyright 2011-2014 Free Software Foundation, Inc.
+
+ Contributed by Andrew Waterman (waterman%cs.berkeley.edu@localhost) at UC Berkeley.
+ Based on MIPS target.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+
+static const bfd_arch_info_type *riscv_compatible
+ (const bfd_arch_info_type *, const bfd_arch_info_type *);
+
+/* The default routine tests bits_per_word, which is wrong on RISC-V, as
+ RISC-V word size doesn't correlate with reloc size. */
+
+static const bfd_arch_info_type *
+riscv_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
+{
+ if (a->arch != b->arch)
+ return NULL;
+
+ /* Machine compatibility is checked in
+ _bfd_riscv_elf_merge_private_bfd_data. */
+
+ return a;
+}
+
+#define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \
+ { \
+ BITS_WORD, /* bits in a word */ \
+ BITS_ADDR, /* bits in an address */ \
+ 8, /* 8 bits in a byte */ \
+ bfd_arch_riscv, \
+ NUMBER, \
+ "riscv", \
+ PRINT, \
+ 3, \
+ DEFAULT, \
+ riscv_compatible, \
+ bfd_default_scan, \
+ bfd_arch_default_fill, \
+ NEXT, \
+ }
+
+enum
+{
+ I_riscv64,
+ I_riscv32
+};
+
+#define NN(index) (&arch_info_struct[(index) + 1])
+
+static const bfd_arch_info_type arch_info_struct[] =
+{
+ N (64, 64, bfd_mach_riscv64, "riscv:rv64", FALSE, NN(I_riscv64)),
+ N (32, 32, bfd_mach_riscv32, "riscv:rv32", FALSE, 0)
+};
+
+/* The default architecture is riscv:rv64. */
+
+const bfd_arch_info_type bfd_riscv_arch =
+N (64, 64, 0, "riscv", TRUE, &arch_info_struct[0]);
diff -r 80f923f79fb2 -r cf48a62b25d4 external/gpl3/binutils/dist/bfd/elf-bfd.h
--- a/external/gpl3/binutils/dist/bfd/elf-bfd.h Fri Sep 19 16:06:16 2014 +0000
+++ b/external/gpl3/binutils/dist/bfd/elf-bfd.h Fri Sep 19 17:19:52 2014 +0000
@@ -423,6 +423,7 @@
OR1K_ELF_DATA,
PPC32_ELF_DATA,
PPC64_ELF_DATA,
+ RISCV_ELF_DATA,
S390_ELF_DATA,
SH_ELF_DATA,
SPARC_ELF_DATA,
diff -r 80f923f79fb2 -r cf48a62b25d4 external/gpl3/binutils/dist/bfd/elf32-riscv.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/external/gpl3/binutils/dist/bfd/elf32-riscv.c Fri Sep 19 17:19:52 2014 +0000
@@ -0,0 +1,193 @@
+/* RISC-V-specific support for 32-bit ELF
+ Copyright 2011-2014 Free Software Foundation, Inc.
+
+ Contributed by Andrew Waterman (waterman%cs.berkeley.edu@localhost) at UC Berkeley.
+ Based on MIPS target.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+
+/* This file handles RISC-V ELF targets. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+#include "bfdlink.h"
+#include "genlink.h"
+#include "elf-bfd.h"
+#include "elfxx-riscv.h"
+#include "elf/riscv.h"
+#include "opcode/riscv.h"
+
+#include "opcode/riscv.h"
+
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