[src/trunk]: src/sys/arch/arm/rockchip Fix aclk_emmc register offset, set RK_...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/1c01e52f908f
branches:  trunk
changeset: 839955:1c01e52f908f
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Wed Mar 13 10:29:56 2019 +0000

description:
Fix aclk_emmc register offset, set RK_COMPOSITE_ROUND_DOWN for SD/EMMC clocks, and add a few more emmc clock nodes

diffstat:

 sys/arch/arm/rockchip/rk3399_cru.c |  17 ++++++++++-------
 1 files changed, 10 insertions(+), 7 deletions(-)

diffs (63 lines):

diff -r b1256ca9432b -r 1c01e52f908f sys/arch/arm/rockchip/rk3399_cru.c
--- a/sys/arch/arm/rockchip/rk3399_cru.c        Wed Mar 13 10:28:37 2019 +0000
+++ b/sys/arch/arm/rockchip/rk3399_cru.c        Wed Mar 13 10:29:56 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: rk3399_cru.c,v 1.5 2019/03/10 11:09:35 jmcneill Exp $ */
+/* $NetBSD: rk3399_cru.c,v 1.6 2019/03/13 10:29:56 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -28,7 +28,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.5 2019/03/10 11:09:35 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.6 2019/03/13 10:29:56 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -594,21 +594,21 @@
                     __BITS(12,8),      /* div_mask */
                     CLKGATE_CON(12),   /* gate_reg */
                     __BIT(13),         /* gate_mask */
-                    0),
+                    RK_COMPOSITE_ROUND_DOWN),
        RK_COMPOSITE(RK3399_SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents,
                     CLKSEL_CON(15),    /* muxdiv_reg */
                     __BITS(10,8),      /* mux_mask */
                     __BITS(6,0),       /* div_mask */
                     CLKGATE_CON(6),    /* gate_reg */
                     __BIT(0),          /* gate_mask */
-                    0),
+                    RK_COMPOSITE_ROUND_DOWN),
        RK_COMPOSITE(RK3399_SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents,
                     CLKSEL_CON(16),    /* muxdiv_reg */
                     __BITS(10,8),      /* mux_mask */
                     __BITS(6,0),       /* div_mask */
                     CLKGATE_CON(6),    /* gate_reg */
                     __BIT(1),          /* gate_mask */
-                    0),
+                    RK_COMPOSITE_ROUND_DOWN),
        RK_GATE(RK3399_HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", CLKGATE_CON(33), 8),
        RK_GATE(RK3399_HCLK_SDIO, "hclk_sdio", "pclk_perilp1", CLKGATE_CON(34), 4),
 
@@ -621,14 +621,17 @@
                     __BITS(6,0),       /* div_mask */
                     CLKGATE_CON(6),    /* gate_reg */
                     __BIT(14),         /* gate_mask */
-                    0),
+                    RK_COMPOSITE_ROUND_DOWN),
        RK_GATE(0, "cpll_aclk_emmc_src", "cpll", CLKGATE_CON(6), 13),
        RK_GATE(0, "gpll_aclk_emmc_src", "gpll", CLKGATE_CON(6), 12),
        RK_COMPOSITE_NOGATE(RK3399_ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_parents,
-                           CLKSEL_CON(22),     /* muxdiv_reg */
+                           CLKSEL_CON(21),     /* muxdiv_reg */
                            __BIT(7),           /* mux_mask */
                            __BITS(4,0),        /* div_mask */
                            0),
+       RK_GATE(RK3399_ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLKGATE_CON(32), 8),
+       RK_GATE(RK3399_ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLKGATE_CON(32), 9),
+       RK_GATE(RK3399_ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLKGATE_CON(32), 10),
 
        /*
         * GMAC