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[src/trunk]: src/sys/arch Add basic support for Allwinner A31.
details: https://anonhg.NetBSD.org/src/rev/510d8da7ac36
branches: trunk
changeset: 825157:510d8da7ac36
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sun Jul 02 00:14:09 2017 +0000
description:
Add basic support for Allwinner A31.
diffstat:
sys/arch/arm/sunxi/files.sunxi | 10 +-
sys/arch/arm/sunxi/sun6i_a31_ccu.c | 277 ++++++++++++++++++++++++++++++++++++
sys/arch/arm/sunxi/sun6i_a31_ccu.h | 250 ++++++++++++++++++++++++++++++++
sys/arch/arm/sunxi/sunxi_ccu.c | 11 +-
sys/arch/arm/sunxi/sunxi_ccu.h | 42 +++++-
sys/arch/arm/sunxi/sunxi_ccu_div.c | 124 ++++++++++++++++
sys/arch/arm/sunxi/sunxi_ccu_nkmp.c | 9 +-
sys/arch/arm/sunxi/sunxi_platform.c | 59 ++++--
sys/arch/arm/sunxi/sunxi_usbphy.c | 30 ++-
sys/arch/evbarm/conf/SUNXI | 13 +-
10 files changed, 780 insertions(+), 45 deletions(-)
diffs (truncated from 1057 to 300 lines):
diff -r 6d105b74f2f9 -r 510d8da7ac36 sys/arch/arm/sunxi/files.sunxi
--- a/sys/arch/arm/sunxi/files.sunxi Sat Jul 01 23:31:19 2017 +0000
+++ b/sys/arch/arm/sunxi/files.sunxi Sun Jul 02 00:14:09 2017 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.sunxi,v 1.6 2017/07/01 16:25:16 jmcneill Exp $
+# $NetBSD: files.sunxi,v 1.7 2017/07/02 00:14:09 jmcneill Exp $
#
# Configuration info for Allwinner sunxi family SoCs
#
@@ -20,11 +20,17 @@
# CCU
define sunxi_ccu
file arch/arm/sunxi/sunxi_ccu.c sunxi_ccu
+file arch/arm/sunxi/sunxi_ccu_div.c sunxi_ccu
file arch/arm/sunxi/sunxi_ccu_gate.c sunxi_ccu
file arch/arm/sunxi/sunxi_ccu_nm.c sunxi_ccu
file arch/arm/sunxi/sunxi_ccu_nkmp.c sunxi_ccu
file arch/arm/sunxi/sunxi_ccu_prediv.c sunxi_ccu
+# CCU (A31)
+device sun6ia31ccu: sunxi_ccu
+attach sun6ia31ccu at fdt with sunxi_a31_ccu
+file arch/arm/sunxi/sun6i_a31_ccu.c sunxi_a31_ccu
+
# CCU (H3)
device sun8ih3ccu: sunxi_ccu
attach sun8ih3ccu at fdt with sunxi_h3_ccu
@@ -71,3 +77,5 @@
defflag opt_soc.h SOC_SUNXI
defflag opt_soc.h SOC_SUN8I: SOC_SUNXI
defflag opt_soc.h SOC_SUN8I_H3: SOC_SUN8I
+defflag opt_soc.h SOC_SUN6I: SOC_SUNXI
+defflag opt_soc.h SOC_SUN6I_A31: SOC_SUN6I
diff -r 6d105b74f2f9 -r 510d8da7ac36 sys/arch/arm/sunxi/sun6i_a31_ccu.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/sunxi/sun6i_a31_ccu.c Sun Jul 02 00:14:09 2017 +0000
@@ -0,0 +1,277 @@
+/* $NetBSD: sun6i_a31_ccu.c,v 1.1 2017/07/02 00:14:09 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
+ * Copyright (c) 2017 Emmanuel Vadot <manu%freebsd.org@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: sun6i_a31_ccu.c,v 1.1 2017/07/02 00:14:09 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/sunxi/sunxi_ccu.h>
+#include <arm/sunxi/sun6i_a31_ccu.h>
+
+#define PLL_PERIPH_CTRL_REG 0x028
+#define AHB1_APB1_CFG_REG 0x054
+#define APB2_CLK_DIV_REG 0x058
+#define AHB1_GATING_REG0 0x060
+#define AHB1_GATING_REG1 0x064
+#define APB1_GATING_REG 0x068
+#define APB2_GATING_REG 0x06c
+#define SD0_CLK_REG 0x088
+#define SD1_CLK_REG 0x08c
+#define SD2_CLK_REG 0x090
+#define SD3_CLK_REG 0x094
+#define USBPHY_CFG_REG 0x0cc
+#define BUS_SOFT_RST_REG0 0x2c0
+#define BUS_SOFT_RST_REG1 0x2c4
+#define BUS_SOFT_RST_REG2 0x2c8
+#define BUS_SOFT_RST_REG3 0x2d0
+#define BUS_SOFT_RST_REG4 0x2d8
+
+static int sun6i_a31_ccu_match(device_t, cfdata_t, void *);
+static void sun6i_a31_ccu_attach(device_t, device_t, void *);
+
+static const char * const compatible[] = {
+ "allwinner,sun6i-a31-ccu",
+ NULL
+};
+
+CFATTACH_DECL_NEW(sunxi_a31_ccu, sizeof(struct sunxi_ccu_softc),
+ sun6i_a31_ccu_match, sun6i_a31_ccu_attach, NULL, NULL);
+
+static struct sunxi_ccu_reset sun6i_a31_ccu_resets[] = {
+ SUNXI_CCU_RESET(A31_RST_USB_PHY0, USBPHY_CFG_REG, 0),
+ SUNXI_CCU_RESET(A31_RST_USB_PHY1, USBPHY_CFG_REG, 1),
+ SUNXI_CCU_RESET(A31_RST_USB_PHY2, USBPHY_CFG_REG, 2),
+
+ SUNXI_CCU_RESET(A31_RST_AHB1_MIPI_DSI, BUS_SOFT_RST_REG0, 1),
+ SUNXI_CCU_RESET(A31_RST_AHB1_SS, BUS_SOFT_RST_REG0, 5),
+ SUNXI_CCU_RESET(A31_RST_AHB1_DMA, BUS_SOFT_RST_REG0, 6),
+ SUNXI_CCU_RESET(A31_RST_AHB1_MMC0, BUS_SOFT_RST_REG0, 8),
+ SUNXI_CCU_RESET(A31_RST_AHB1_MMC1, BUS_SOFT_RST_REG0, 9),
+ SUNXI_CCU_RESET(A31_RST_AHB1_MMC2, BUS_SOFT_RST_REG0, 10),
+ SUNXI_CCU_RESET(A31_RST_AHB1_MMC3, BUS_SOFT_RST_REG0, 11),
+ SUNXI_CCU_RESET(A31_RST_AHB1_NAND1, BUS_SOFT_RST_REG0, 12),
+ SUNXI_CCU_RESET(A31_RST_AHB1_NAND0, BUS_SOFT_RST_REG0, 13),
+ SUNXI_CCU_RESET(A31_RST_AHB1_SDRAM, BUS_SOFT_RST_REG0, 14),
+ SUNXI_CCU_RESET(A31_RST_AHB1_EMAC, BUS_SOFT_RST_REG0, 17),
+ SUNXI_CCU_RESET(A31_RST_AHB1_TS, BUS_SOFT_RST_REG0, 18),
+ SUNXI_CCU_RESET(A31_RST_AHB1_HSTIMER, BUS_SOFT_RST_REG0, 19),
+ SUNXI_CCU_RESET(A31_RST_AHB1_SPI0, BUS_SOFT_RST_REG0, 20),
+ SUNXI_CCU_RESET(A31_RST_AHB1_SPI1, BUS_SOFT_RST_REG0, 21),
+ SUNXI_CCU_RESET(A31_RST_AHB1_SPI2, BUS_SOFT_RST_REG0, 22),
+ SUNXI_CCU_RESET(A31_RST_AHB1_SPI3, BUS_SOFT_RST_REG0, 23),
+ SUNXI_CCU_RESET(A31_RST_AHB1_OTG, BUS_SOFT_RST_REG0, 24),
+ SUNXI_CCU_RESET(A31_RST_AHB1_EHCI0, BUS_SOFT_RST_REG0, 26),
+ SUNXI_CCU_RESET(A31_RST_AHB1_EHCI1, BUS_SOFT_RST_REG0, 27),
+ SUNXI_CCU_RESET(A31_RST_AHB1_OHCI0, BUS_SOFT_RST_REG0, 29),
+ SUNXI_CCU_RESET(A31_RST_AHB1_OHCI1, BUS_SOFT_RST_REG0, 30),
+ SUNXI_CCU_RESET(A31_RST_AHB1_OHCI2, BUS_SOFT_RST_REG0, 31),
+
+ SUNXI_CCU_RESET(A31_RST_AHB1_VE, BUS_SOFT_RST_REG1, 0),
+ SUNXI_CCU_RESET(A31_RST_AHB1_LCD0, BUS_SOFT_RST_REG1, 4),
+ SUNXI_CCU_RESET(A31_RST_AHB1_LCD1, BUS_SOFT_RST_REG1, 5),
+ SUNXI_CCU_RESET(A31_RST_AHB1_CSI, BUS_SOFT_RST_REG1, 8),
+ SUNXI_CCU_RESET(A31_RST_AHB1_HDMI, BUS_SOFT_RST_REG1, 11),
+ SUNXI_CCU_RESET(A31_RST_AHB1_BE0, BUS_SOFT_RST_REG1, 12),
+ SUNXI_CCU_RESET(A31_RST_AHB1_BE1, BUS_SOFT_RST_REG1, 13),
+ SUNXI_CCU_RESET(A31_RST_AHB1_FE0, BUS_SOFT_RST_REG1, 14),
+ SUNXI_CCU_RESET(A31_RST_AHB1_FE1, BUS_SOFT_RST_REG1, 15),
+ SUNXI_CCU_RESET(A31_RST_AHB1_MP, BUS_SOFT_RST_REG1, 16),
+ SUNXI_CCU_RESET(A31_RST_AHB1_GPU, BUS_SOFT_RST_REG1, 20),
+ SUNXI_CCU_RESET(A31_RST_AHB1_DEU0, BUS_SOFT_RST_REG1, 23),
+ SUNXI_CCU_RESET(A31_RST_AHB1_DEU1, BUS_SOFT_RST_REG1, 24),
+ SUNXI_CCU_RESET(A31_RST_AHB1_DRC0, BUS_SOFT_RST_REG1, 25),
+ SUNXI_CCU_RESET(A31_RST_AHB1_DRC1, BUS_SOFT_RST_REG1, 26),
+
+ SUNXI_CCU_RESET(A31_RST_AHB1_LVDS, BUS_SOFT_RST_REG2, 0),
+
+ SUNXI_CCU_RESET(A31_RST_APB1_CODEC, BUS_SOFT_RST_REG3, 0),
+ SUNXI_CCU_RESET(A31_RST_APB1_SPDIF, BUS_SOFT_RST_REG3, 1),
+ SUNXI_CCU_RESET(A31_RST_APB1_DIGITAL_MIC, BUS_SOFT_RST_REG3, 4),
+ SUNXI_CCU_RESET(A31_RST_APB1_DAUDIO0, BUS_SOFT_RST_REG3, 12),
+ SUNXI_CCU_RESET(A31_RST_APB1_DAUDIO1, BUS_SOFT_RST_REG3, 13),
+
+ SUNXI_CCU_RESET(A31_RST_APB2_I2C0, BUS_SOFT_RST_REG4, 0),
+ SUNXI_CCU_RESET(A31_RST_APB2_I2C1, BUS_SOFT_RST_REG4, 1),
+ SUNXI_CCU_RESET(A31_RST_APB2_I2C2, BUS_SOFT_RST_REG4, 2),
+ SUNXI_CCU_RESET(A31_RST_APB2_I2C3, BUS_SOFT_RST_REG4, 3),
+ SUNXI_CCU_RESET(A31_RST_APB2_UART0, BUS_SOFT_RST_REG4, 16),
+ SUNXI_CCU_RESET(A31_RST_APB2_UART1, BUS_SOFT_RST_REG4, 17),
+ SUNXI_CCU_RESET(A31_RST_APB2_UART2, BUS_SOFT_RST_REG4, 18),
+ SUNXI_CCU_RESET(A31_RST_APB2_UART3, BUS_SOFT_RST_REG4, 19),
+ SUNXI_CCU_RESET(A31_RST_APB2_UART4, BUS_SOFT_RST_REG4, 20),
+ SUNXI_CCU_RESET(A31_RST_APB2_UART5, BUS_SOFT_RST_REG4, 21),
+};
+
+static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph" };
+static const char *apb1_parents[] = { "ahb1" };
+static const char *apb2_parents[] = { "losc", "hosc", "pll_periph", "pll_periph" };
+static const char *mod_parents[] = { "hosc", "pll_periph" };
+
+static struct sunxi_ccu_clk sun6i_a31_ccu_clks[] = {
+ SUNXI_CCU_NKMP(A31_CLK_PLL_PERIPH, "pll_periph", "hosc",
+ PLL_PERIPH_CTRL_REG, /* reg */
+ __BITS(12,8), /* n */
+ __BITS(5,4), /* k */
+ 0, /* m */
+ 0, /* p */
+ __BIT(31), /* enable */
+ SUNXI_CCU_NKMP_DIVIDE_BY_TWO),
+
+ SUNXI_CCU_DIV(A31_CLK_APB1, "apb1", apb1_parents,
+ AHB1_APB1_CFG_REG, /* reg */
+ __BITS(9,8), /* div */
+ 0, /* sel */
+ SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE),
+
+ SUNXI_CCU_PREDIV(A31_CLK_AHB1, "ahb1", ahb1_parents,
+ AHB1_APB1_CFG_REG, /* reg */
+ __BITS(7,6), /* prediv */
+ __BIT(3), /* prediv_sel */
+ __BITS(5,4), /* div */
+ __BITS(13,12), /* sel */
+ SUNXI_CCU_PREDIV_POWER_OF_TWO),
+
+ SUNXI_CCU_NM(A31_CLK_APB2, "apb2", apb2_parents,
+ APB2_CLK_DIV_REG, /* reg */
+ __BITS(17,16), /* n */
+ __BITS(4,0), /* m */
+ __BITS(25,24), /* sel */
+ 0, /* enable */
+ SUNXI_CCU_NM_POWER_OF_TWO),
+
+ SUNXI_CCU_NM(A31_CLK_MMC0, "mmc0", mod_parents,
+ SD0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+ SUNXI_CCU_NM(A31_CLK_MMC1, "mmc1", mod_parents,
+ SD1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+ SUNXI_CCU_NM(A31_CLK_MMC2, "mmc2", mod_parents,
+ SD2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+ SUNXI_CCU_NM(A31_CLK_MMC3, "mmc3", mod_parents,
+ SD3_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31),
+ SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN),
+
+ SUNXI_CCU_GATE(A31_CLK_AHB1_MMC0, "ahb1-mmc0", "ahb1",
+ AHB1_GATING_REG0, 8),
+ SUNXI_CCU_GATE(A31_CLK_AHB1_MMC1, "ahb1-mmc1", "ahb1",
+ AHB1_GATING_REG0, 9),
+ SUNXI_CCU_GATE(A31_CLK_AHB1_MMC2, "ahb1-mmc2", "ahb1",
+ AHB1_GATING_REG0, 10),
+ SUNXI_CCU_GATE(A31_CLK_AHB1_MMC3, "ahb1-mmc3", "ahb1",
+ AHB1_GATING_REG0, 11),
+ SUNXI_CCU_GATE(A31_CLK_AHB1_EMAC, "ahb1-emac", "ahb1",
+ AHB1_GATING_REG0, 17),
+ SUNXI_CCU_GATE(A31_CLK_AHB1_OTG, "ahb1-otg", "ahb1",
+ AHB1_GATING_REG0, 24),
+ SUNXI_CCU_GATE(A31_CLK_AHB1_EHCI0, "ahb1-ehci0", "ahb1",
+ AHB1_GATING_REG0, 26),
+ SUNXI_CCU_GATE(A31_CLK_AHB1_EHCI1, "ahb1-ehci1", "ahb1",
+ AHB1_GATING_REG0, 27),
+ SUNXI_CCU_GATE(A31_CLK_AHB1_OHCI0, "ahb1-ohci0", "ahb1",
+ AHB1_GATING_REG0, 29),
+ SUNXI_CCU_GATE(A31_CLK_AHB1_OHCI1, "ahb1-ohci1", "ahb1",
+ AHB1_GATING_REG0, 30),
+ SUNXI_CCU_GATE(A31_CLK_AHB1_OHCI2, "ahb1-ohci2", "ahb1",
+ AHB1_GATING_REG0, 31),
+
+ SUNXI_CCU_GATE(A31_CLK_APB2_I2C0, "apb2-i2c0", "apb2",
+ APB2_GATING_REG, 0),
+ SUNXI_CCU_GATE(A31_CLK_APB2_I2C1, "apb2-i2c1", "apb2",
+ APB2_GATING_REG, 1),
+ SUNXI_CCU_GATE(A31_CLK_APB2_I2C2, "apb2-i2c2", "apb2",
+ APB2_GATING_REG, 2),
+ SUNXI_CCU_GATE(A31_CLK_APB2_I2C3, "apb2-i2c3", "apb2",
+ APB2_GATING_REG, 3),
+ SUNXI_CCU_GATE(A31_CLK_APB2_UART0, "apb2-uart0", "apb2",
+ APB2_GATING_REG, 16),
+ SUNXI_CCU_GATE(A31_CLK_APB2_UART1, "apb2-uart1", "apb2",
+ APB2_GATING_REG, 17),
+ SUNXI_CCU_GATE(A31_CLK_APB2_UART2, "apb2-uart2", "apb2",
+ APB2_GATING_REG, 18),
+ SUNXI_CCU_GATE(A31_CLK_APB2_UART3, "apb2-uart3", "apb2",
+ APB2_GATING_REG, 19),
+ SUNXI_CCU_GATE(A31_CLK_APB2_UART4, "apb2-uart4", "apb2",
+ APB2_GATING_REG, 20),
+ SUNXI_CCU_GATE(A31_CLK_APB2_UART5, "apb2-uart5", "apb2",
+ APB2_GATING_REG, 21),
+
+ SUNXI_CCU_GATE(A31_CLK_USB_PHY0, "usb-phy0", "hosc",
+ USBPHY_CFG_REG, 8),
+ SUNXI_CCU_GATE(A31_CLK_USB_PHY1, "usb-phy1", "hosc",
+ USBPHY_CFG_REG, 9),
+ SUNXI_CCU_GATE(A31_CLK_USB_PHY2, "usb-phy2", "hosc",
+ USBPHY_CFG_REG, 10),
+ SUNXI_CCU_GATE(A31_CLK_USB_OHCI0, "usb-ohci0", "hosc",
+ USBPHY_CFG_REG, 16),
+ SUNXI_CCU_GATE(A31_CLK_USB_OHCI1, "usb-ohci1", "hosc",
+ USBPHY_CFG_REG, 17),
+ SUNXI_CCU_GATE(A31_CLK_USB_OHCI2, "usb-ohci2", "hosc",
+ USBPHY_CFG_REG, 18),
+};
+
+static int
+sun6i_a31_ccu_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+sun6i_a31_ccu_attach(device_t parent, device_t self, void *aux)
+{
+ struct sunxi_ccu_softc * const sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+
+ sc->sc_dev = self;
+ sc->sc_phandle = faa->faa_phandle;
+ sc->sc_bst = faa->faa_bst;
+
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