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[src/trunk]: src/sys/arch Add Exynos 5410 clock controller driver.
details: https://anonhg.NetBSD.org/src/rev/65f49e019b04
branches: trunk
changeset: 824839:65f49e019b04
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Tue Jun 20 13:21:45 2017 +0000
description:
Add Exynos 5410 clock controller driver.
diffstat:
sys/arch/arm/samsung/exynos5410_clock.c | 864 ++++++++++++++++++++++++++++++++
sys/arch/arm/samsung/files.exynos | 6 +-
sys/arch/evbarm/conf/EXYNOS | 3 +-
3 files changed, 871 insertions(+), 2 deletions(-)
diffs (truncated from 903 to 300 lines):
diff -r 4db5fe60c094 -r 65f49e019b04 sys/arch/arm/samsung/exynos5410_clock.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/samsung/exynos5410_clock.c Tue Jun 20 13:21:45 2017 +0000
@@ -0,0 +1,864 @@
+/* $NetBSD: exynos5410_clock.c,v 1.1 2017/06/20 13:21:45 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015-2017 Jared McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: exynos5410_clock.c,v 1.1 2017/06/20 13:21:45 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/atomic.h>
+
+#include <dev/clk/clk_backend.h>
+
+#include <arm/samsung/exynos_reg.h>
+#include <arm/samsung/exynos_var.h>
+#include <arm/samsung/exynos_clock.h>
+
+#include <dev/fdt/fdtvar.h>
+
+static struct clk *exynos5410_clock_decode(device_t, const void *, size_t);
+
+static const struct fdtbus_clock_controller_func exynos5410_car_fdtclock_funcs = {
+ .decode = exynos5410_clock_decode
+};
+
+/* DT clock ID to clock name mappings */
+static struct exynos5410_clock_id {
+ u_int id;
+ const char *name;
+} exynos5410_clock_ids[] = {
+ /* core clocks */
+ { 1, "fin_pll" },
+ { 2, "fout_apll" },
+ { 3, "fout_cpll" },
+ { 4, "fout_dpll" },
+ { 5, "fout_mpll" },
+ { 6, "fout_kpll" },
+ { 7, "fout_epll" },
+
+ /* gate for special clocks (sclk) */
+ { 128, "sclk_uart0" },
+ { 129, "sclk_uart1" },
+ { 130, "sclk_uart2" },
+ { 131, "sclk_uart3" },
+ { 132, "sclk_mmc0" },
+ { 133, "sclk_mmc1" },
+ { 134, "sclk_mmc2" },
+ { 150, "sclk_usbd300" },
+ { 151, "sclk_usbd301" },
+ { 152, "sclk_usbphy300" },
+ { 153, "sclk_usbphy301" },
+ { 155, "sclk_pwm" },
+
+ /* gate clocks */
+ { 257, "uart0" },
+ { 258, "uart1" },
+ { 259, "uart2" },
+ { 260, "uart3" },
+ { 261, "i2c0" },
+ { 262, "i2c1" },
+ { 263, "i2c2" },
+ { 264, "i2c3" },
+ { 265, "usi0" },
+ { 266, "usi1" },
+ { 267, "usi2" },
+ { 268, "usi3" },
+ { 279, "pwm" },
+ { 315, "mct" },
+ { 316, "wdt" },
+ { 317, "rtc" },
+ { 318, "tmu" },
+ { 351, "mmc0" },
+ { 352, "mmc1" },
+ { 353, "mmc2" },
+ { 362, "pdma0" },
+ { 363, "pdma1" },
+ { 365, "usbh20" },
+ { 366, "usbd300" },
+ { 367, "usbd301" },
+ { 471, "sss" },
+};
+
+static struct clk *exynos5410_clock_get(void *, const char *);
+static void exynos5410_clock_put(void *, struct clk *);
+static u_int exynos5410_clock_get_rate(void *, struct clk *);
+static int exynos5410_clock_set_rate(void *, struct clk *, u_int);
+static int exynos5410_clock_enable(void *, struct clk *);
+static int exynos5410_clock_disable(void *, struct clk *);
+static int exynos5410_clock_set_parent(void *, struct clk *, struct clk *);
+static struct clk *exynos5410_clock_get_parent(void *, struct clk *);
+
+static const struct clk_funcs exynos5410_clock_funcs = {
+ .get = exynos5410_clock_get,
+ .put = exynos5410_clock_put,
+ .get_rate = exynos5410_clock_get_rate,
+ .set_rate = exynos5410_clock_set_rate,
+ .enable = exynos5410_clock_enable,
+ .disable = exynos5410_clock_disable,
+ .set_parent = exynos5410_clock_set_parent,
+ .get_parent = exynos5410_clock_get_parent,
+};
+
+#define CLK_FIXED(_name, _rate) { \
+ .base = { .name = (_name) }, .type = EXYNOS_CLK_FIXED, \
+ .u = { .fixed = { .rate = (_rate) } } \
+}
+
+#define CLK_PLL(_name, _parent, _lock, _con0) { \
+ .base = { .name = (_name) }, .type = EXYNOS_CLK_PLL, \
+ .parent = (_parent), \
+ .u = { \
+ .pll = { \
+ .lock_reg = (_lock), \
+ .con0_reg = (_con0), \
+ } \
+ } \
+}
+
+#define CLK_MUXF(_name, _alias, _reg, _bits, _f, _p) { \
+ .base = { .name = (_name), .flags = (_f) }, \
+ .type = EXYNOS_CLK_MUX, \
+ .alias = (_alias), \
+ .u = { \
+ .mux = { \
+ .nparents = __arraycount(_p), \
+ .parents = (_p), \
+ .reg = (_reg), \
+ .bits = (_bits) \
+ } \
+ } \
+}
+
+#define CLK_MUXA(_name, _alias, _reg, _bits, _p) \
+ CLK_MUXF(_name, _alias, _reg, _bits, 0, _p)
+
+#define CLK_MUX(_name, _reg, _bits, _p) \
+ CLK_MUXF(_name, NULL, _reg, _bits, 0, _p)
+
+#define CLK_DIVF(_name, _parent, _reg, _bits, _f) { \
+ .base = { .name = (_name), .flags = (_f) }, \
+ .type = EXYNOS_CLK_DIV, \
+ .parent = (_parent), \
+ .u = { \
+ .div = { \
+ .reg = (_reg), \
+ .bits = (_bits) \
+ } \
+ } \
+}
+
+#define CLK_DIV(_name, _parent, _reg, _bits) \
+ CLK_DIVF(_name, _parent, _reg, _bits, 0)
+
+#define CLK_GATE(_name, _parent, _reg, _bits, _f) { \
+ .base = { .name = (_name), .flags = (_f) }, \
+ .type = EXYNOS_CLK_GATE, \
+ .parent = (_parent), \
+ .u = { \
+ .gate = { \
+ .reg = (_reg), \
+ .bits = (_bits) \
+ } \
+ } \
+}
+
+#define EXYNOS5410_APLL_LOCK 0x00000
+#define EXYNOS5410_APLL_CON0 0x00100
+#define EXYNOS5410_MPLL_LOCK 0x04000
+#define EXYNOS5410_MPLL_CON0 0x04100
+#define EXYNOS5410_CPLL_LOCK 0x10020
+#define EXYNOS5410_EPLL_LOCK 0x10040
+#define EXYNOS5410_CPLL_CON0 0x10120
+#define EXYNOS5410_EPLL_CON0 0x10130
+#define EXYNOS5410_EPLL_CON1 0x10134
+#define EXYNOS5410_EPLL_CON2 0x10138
+#define EXYNOS5410_BPLL_LOCK 0x20010
+#define EXYNOS5410_BPLL_CON0 0x20110
+#define EXYNOS5410_KPLL_LOCK 0x28000
+#define EXYNOS5410_KPLL_CON0 0x28100
+
+#define EXYNOS5410_SRC_CPU 0x00200
+#define EXYNOS5410_SRC_CPERI1 0x04204
+#define EXYNOS5410_SRC_TOP0 0x10210
+#define EXYNOS5410_SRC_TOP1 0x10214
+#define EXYNOS5410_SRC_TOP2 0x10218
+#define EXYNOS5410_SRC_FSYS 0x10244
+#define EXYNOS5410_SRC_PERIC0 0x10250
+#define EXYNOS5410_SRC_MASK_FSYS 0x10340
+#define EXYNOS5410_SRC_MASK_PERIC0 0x10350
+#define EXYNOS5410_SRC_CDREX 0x20200
+#define EXYNOS5410_SRC_KFC 0x28200
+
+#define EXYNOS5410_DIV_CPU0 0x00500
+#define EXYNOS5410_DIV_TOP0 0x10510
+#define EXYNOS5410_DIV_TOP1 0x10514
+#define EXYNOS5410_DIV_FSYS0 0x10548
+#define EXYNOS5410_DIV_FSYS1 0x1054c
+#define EXYNOS5410_DIV_FSYS2 0x10550
+#define EXYNOS5410_DIV_PERIC0 0x10558
+#define EXYNOS5410_DIV_PERIC3 0x10564
+#define EXYNOS5410_DIV_KFC0 0x28500
+
+#define EXYNOS5410_GATE_IP_G2D 0x08800
+#define EXYNOS5410_GATE_BUS_FSYS0 0x10740
+#define EXYNOS5410_GATE_TOP_SCLK_FSYS 0x10840
+#define EXYNOS5410_GATE_TOP_SCLK_PERIC 0x10850
+#define EXYNOS5410_GATE_IP_FSYS 0x10944
+#define EXYNOS5410_GATE_IP_PERIC 0x10950
+#define EXYNOS5410_GATE_IP_PERIS 0x10960
+
+static const char *mout_apll_p[] = { "fin_pll", "fout_apll" };
+static const char *mout_bpll_p[] = { "fin_pll", "fout_bpll" };
+static const char *mout_cpll_p[] = { "fin_pll", "fout_cpll" };
+static const char *mout_epll_p[] = { "fin_pll", "fout_epll" };
+static const char *mout_mpll_p[] = { "fin_pll", "fout_mpll" };
+static const char *mout_kpll_p[] = { "fin_pll", "fout_kpll" };
+
+static const char *mout_cpu_p[] = { "mout_apll", "sclk_mpll" };
+static const char *mout_kfc_p[] = { "mout_kpll", "sclk_mpll" };
+
+static const char *mout_mpll_user_p[] = { "fin_pll", "sclk_mpll" };
+static const char *mout_bpll_user_p[] = { "fin_pll", "sclk_bpll" };
+static const char *mout_mpll_bpll_p[] =
+ { "sclk_mpll_muxed", "sclk_bpll_muxed" };
+static const char *mout_sclk_mpll_bpll_p[] = { "sclk_mpll_bpll", "fin_pll" };
+
+static const char *mout_group2_p[] =
+ { "fin_pll", "fin_pll", "none", "none", "none", "none",
+ "sclk_mpll_bpll", "none", "none", "sclk_cpll" };
+
+static struct exynos_clk exynos5410_clocks[] = {
+ CLK_FIXED("fin_pll", EXYNOS_F_IN_FREQ),
+
+ CLK_PLL("fout_apll", "fin_pll", EXYNOS5410_APLL_LOCK,
+ EXYNOS5410_APLL_CON0),
+ CLK_PLL("fout_bpll", "fin_pll", EXYNOS5410_BPLL_LOCK,
+ EXYNOS5410_BPLL_CON0),
+ CLK_PLL("fout_cpll", "fin_pll", EXYNOS5410_CPLL_LOCK,
+ EXYNOS5410_CPLL_CON0),
+ CLK_PLL("fout_epll", "fin_pll", EXYNOS5410_EPLL_LOCK,
+ EXYNOS5410_EPLL_CON0),
+ CLK_PLL("fout_mpll", "fin_pll", EXYNOS5410_MPLL_LOCK,
+ EXYNOS5410_MPLL_CON0),
+ CLK_PLL("fout_kpll", "fin_pll", EXYNOS5410_KPLL_LOCK,
+ EXYNOS5410_KPLL_CON0),
+
+ CLK_MUX("mout_apll", EXYNOS5410_SRC_CPU, __BIT(0), mout_apll_p),
+ CLK_MUX("mout_cpu", EXYNOS5410_SRC_CPU, __BIT(16), mout_cpu_p),
+ CLK_MUX("mout_kpll", EXYNOS5410_SRC_KFC, __BIT(0), mout_kpll_p),
+ CLK_MUX("mout_kfc", EXYNOS5410_SRC_KFC, __BIT(16), mout_kfc_p),
+
+ CLK_MUX("sclk_mpll", EXYNOS5410_SRC_CPERI1, __BIT(8), mout_mpll_p),
+ CLK_MUX("sclk_mpll_muxed", EXYNOS5410_SRC_TOP2, __BIT(20), mout_mpll_user_p),
+ CLK_MUX("sclk_bpll", EXYNOS5410_SRC_CDREX, __BIT(0), mout_bpll_p),
+ CLK_MUX("sclk_bpll_muxed", EXYNOS5410_SRC_TOP2, __BIT(24), mout_bpll_user_p),
+ CLK_MUX("sclk_epll", EXYNOS5410_SRC_TOP2, __BIT(12), mout_epll_p),
+ CLK_MUX("sclk_cpll", EXYNOS5410_SRC_TOP2, __BIT(8), mout_cpll_p),
+ CLK_MUX("sclk_mpll_bpll", EXYNOS5410_SRC_TOP1, __BIT(20), mout_mpll_bpll_p),
+
+ CLK_MUX("mout_mmc0", EXYNOS5410_SRC_FSYS, __BITS(3,0), mout_group2_p),
+ CLK_MUX("mout_mmc1", EXYNOS5410_SRC_FSYS, __BITS(7,4), mout_group2_p),
+ CLK_MUX("mout_mmc2", EXYNOS5410_SRC_FSYS, __BITS(11,8), mout_group2_p),
+ CLK_MUX("mout_usbd300", EXYNOS5410_SRC_FSYS, __BIT(28), mout_sclk_mpll_bpll_p),
+ CLK_MUX("mout_usbd301", EXYNOS5410_SRC_FSYS, __BIT(29), mout_sclk_mpll_bpll_p),
+ CLK_MUX("mout_uart0", EXYNOS5410_SRC_PERIC0, __BITS(3,0), mout_group2_p),
+ CLK_MUX("mout_uart1", EXYNOS5410_SRC_PERIC0, __BITS(7,4), mout_group2_p),
+ CLK_MUX("mout_uart2", EXYNOS5410_SRC_PERIC0, __BITS(11,8), mout_group2_p),
+ CLK_MUX("mout_uart3", EXYNOS5410_SRC_PERIC0, __BITS(15,12), mout_group2_p),
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