[src/trunk]: src/sys/arch/arm Fixup the compile time decisions around PMAP_{I...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/4002f05ae51c
branches:  trunk
changeset: 821960:4002f05ae51c
user:      skrll <skrll%NetBSD.org@localhost>
date:      Thu Feb 23 08:22:20 2017 +0000

description:
Fixup the compile time decisions around PMAP_{INCLUDE,NEEDS}_PTE_SYNC and
fix the options for xscale boards which require the code in
pmap_l2ptp_ctor marked as #ifndef PMAP_INCLUDE_PTE_SYNC.

Fix the typo (pte -> opte) in this code block and consistently use opte
elsewhere.

PR/51990: Regression data_abort_handler: data_aborts fsr=0x406 far=0xbfffeff5  on copyout in init

diffstat:

 sys/arch/arm/arm32/pmap.c         |  12 ++++++------
 sys/arch/arm/include/arm32/pmap.h |  18 ++++++++++++------
 2 files changed, 18 insertions(+), 12 deletions(-)

diffs (90 lines):

diff -r dbaa97c2e39e -r 4002f05ae51c sys/arch/arm/arm32/pmap.c
--- a/sys/arch/arm/arm32/pmap.c Thu Feb 23 08:11:09 2017 +0000
+++ b/sys/arch/arm/arm32/pmap.c Thu Feb 23 08:22:20 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.c,v 1.342 2016/12/23 07:15:27 cherry Exp $        */
+/*     $NetBSD: pmap.c,v 1.343 2017/02/23 08:22:20 skrll Exp $ */
 
 /*
  * Copyright 2003 Wasabi Systems, Inc.
@@ -217,7 +217,7 @@
 
 #include <arm/locore.h>
 
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.342 2016/12/23 07:15:27 cherry Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.343 2017/02/23 08:22:20 skrll Exp $");
 
 //#define PMAP_DEBUG
 #ifdef PMAP_DEBUG
@@ -1694,7 +1694,7 @@
                        /*
                         * Page tables must have the cache-mode set correctly.
                         */
-                       const pt_entry_t npte = (pte & ~L2_S_CACHE_MASK)
+                       const pt_entry_t npte = (opte & ~L2_S_CACHE_MASK)
                            | pte_l2_s_cache_mode_pt;
                        l2pte_set(ptep, npte, opte);
                        PTE_SYNC(ptep);
@@ -1973,7 +1973,7 @@
                        pt_entry_t npte = opte & ~L2_S_CACHE_MASK;
 
                        if ((va != pv->pv_va || pm != pv->pv_pmap)
-                           && l2pte_valid_p(npte)) {
+                           && l2pte_valid_p(opte)) {
 #ifdef PMAP_CACHE_VIVT
                                pmap_cache_wbinv_page(pv->pv_pmap, pv->pv_va,
                                    true, pv->pv_flags);
@@ -2301,7 +2301,7 @@
                if (opte == npte)       /* only update is there's a change */
                        continue;
 
-               if (l2pte_valid_p(npte)) {
+               if (l2pte_valid_p(opte)) {
                        pmap_tlb_flush_SE(pv->pv_pmap, pv->pv_va, pv->pv_flags);
                }
 
@@ -4275,7 +4275,7 @@
        if ((opte & L2_S_PROT_U) == 0 || (opte & L2_XS_XN) == 0)
                goto out;
 
-       paddr_t pa = l2pte_pa(pte);
+       paddr_t pa = l2pte_pa(opte);
        struct vm_page * const pg = PHYS_TO_VM_PAGE(pa);
        KASSERT(pg != NULL);
 
diff -r dbaa97c2e39e -r 4002f05ae51c sys/arch/arm/include/arm32/pmap.h
--- a/sys/arch/arm/include/arm32/pmap.h Thu Feb 23 08:11:09 2017 +0000
+++ b/sys/arch/arm/include/arm32/pmap.h Thu Feb 23 08:22:20 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.h,v 1.144 2016/07/14 05:00:51 skrll Exp $ */
+/*     $NetBSD: pmap.h,v 1.145 2017/02/23 08:22:20 skrll Exp $ */
 
 /*
  * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@@ -480,15 +480,21 @@
 extern int pmap_needs_pte_sync;
 #if defined(_KERNEL_OPT)
 /*
+ * Perform compile time evaluation of PMAP_NEEDS_PTE_SYNC when only a
+ * single MMU type is selected.
+ *
  * StrongARM SA-1 caches do not have a write-through mode.  So, on these,
- * we need to do PTE syncs.  If only SA-1 is configured, then evaluate
- * this at compile time.
+ * we need to do PTE syncs. Additionally, V6 MMUs also need PTE syncs.
+ * Finally, MEMC, GENERIC and XSCALE MMUs do not need PTE syncs.
+ *
+ * Use run time evaluation for all other cases.
+ * 
  */
-#if (ARM_MMU_SA1 + ARM_MMU_V6 != 0) && (ARM_NMMUS == 1)
+#if (ARM_NMMUS == 1)
+#if (ARM_MMU_SA1 + ARM_MMU_V6 != 0)
 #define        PMAP_INCLUDE_PTE_SYNC
-#if (ARM_MMU_V6 > 0)
 #define        PMAP_NEEDS_PTE_SYNC     1
-#elif (ARM_MMU_SA1 == 0)
+#elif (ARM_MMU_MEMC + ARM_MMU_GENERIC + ARM_MMU_XSCALE != 0)
 #define        PMAP_NEEDS_PTE_SYNC     0
 #endif
 #endif