[src/trunk]: src/sys/arch/arm/nvidia Explicitly initialize interrupt controll...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/2294976bf0a7
branches:  trunk
changeset: 823428:2294976bf0a7
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sat Apr 22 19:20:51 2017 +0000

description:
Explicitly initialize interrupt controllers and since we pass through to
GIC, don't include "LIC" in interrupt string.

diffstat:

 sys/arch/arm/nvidia/tegra_lic.c |  36 ++++++++++++++++++++++++++++++++----
 1 files changed, 32 insertions(+), 4 deletions(-)

diffs (78 lines):

diff -r d7178738e1b0 -r 2294976bf0a7 sys/arch/arm/nvidia/tegra_lic.c
--- a/sys/arch/arm/nvidia/tegra_lic.c   Sat Apr 22 17:41:20 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra_lic.c   Sat Apr 22 19:20:51 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_lic.c,v 1.3 2016/01/05 21:53:48 marty Exp $ */
+/* $NetBSD: tegra_lic.c,v 1.4 2017/04/22 19:20:51 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_lic.c,v 1.3 2016/01/05 21:53:48 marty Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_lic.c,v 1.4 2017/04/22 19:20:51 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -44,6 +44,9 @@
 
 #include <dev/fdt/fdtvar.h>
 
+#define        LIC_CPU_IER_CLR_REG     0x28
+#define        LIC_CPU_IEP_CLASS_REG   0x2c
+
 static int     tegra_lic_match(device_t, cfdata_t, void *);
 static void    tegra_lic_attach(device_t, device_t, void *);
 
@@ -80,7 +83,11 @@
 {
        struct tegra_lic_softc * const sc = device_private(self);
        struct fdt_attach_args * const faa = aux;
-       int error;
+       bus_space_tag_t bst;
+       bus_space_handle_t bsh;
+       bus_addr_t addr;
+       bus_size_t size;
+       int error, index;
 
        sc->sc_dev = self;
        sc->sc_phandle = faa->faa_phandle;
@@ -94,6 +101,27 @@
 
        aprint_naive("\n");
        aprint_normal(": LIC\n");
+
+       bst = faa->faa_bst;
+       for (index = 0; ; index++) {
+               error = fdtbus_get_reg(faa->faa_phandle, index, &addr, &size);
+               if (error != 0)
+                       break;
+               error = bus_space_map(bst, addr, size, 0, &bsh);
+               if (error) {
+                       aprint_error_dev(self, "can't map IC#%d: %d\n",
+                           index, error);
+                       continue;
+               }
+
+               /* Clear interrupt enable for CPU */
+               bus_space_write_4(bst, bsh, LIC_CPU_IER_CLR_REG, 0xffffffff);
+
+               /* Route to IRQ */
+               bus_space_write_4(bst, bsh, LIC_CPU_IEP_CLASS_REG, 0);
+
+               bus_space_unmap(bst, bsh, size);
+       }
 }
 
 static void *
@@ -133,7 +161,7 @@
        const u_int intr = be32toh(specifier[1]);
        const u_int irq = type == 0 ? IRQ_SPI(intr) : IRQ_PPI(intr);
 
-       snprintf(buf, buflen, "LIC irq %d", irq);
+       snprintf(buf, buflen, "irq %d", irq);
 
        return true;
 }