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[src/trunk]: src/sys Add support for multiple clock domains in clk API.
details: https://anonhg.NetBSD.org/src/rev/9cc784ee6cd0
branches: trunk
changeset: 823209:9cc784ee6cd0
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sun Apr 16 12:28:21 2017 +0000
description:
Add support for multiple clock domains in clk API.
diffstat:
sys/arch/arm/nvidia/tegra124_car.c | 71 ++++++++++++++++++++++++++++++++---
sys/arch/arm/nvidia/tegra_ahcisata.c | 26 ++-----------
sys/arch/arm/nvidia/tegra_drm.c | 23 +----------
sys/arch/arm/nvidia/tegra_hdaudio.c | 22 +----------
sys/arch/arm/nvidia/tegra_soctherm.c | 36 +++---------------
sys/arch/arm/nvidia/tegra_timer.c | 36 +++++++----------
sys/arch/arm/nvidia/tegra_xusb.c | 27 +------------
sys/dev/clk/clk.c | 55 ++++++++++++---------------
sys/dev/clk/clk.h | 5 +-
sys/dev/clk/clk_backend.h | 10 +++-
10 files changed, 132 insertions(+), 179 deletions(-)
diffs (truncated from 744 to 300 lines):
diff -r 863662db4032 -r 9cc784ee6cd0 sys/arch/arm/nvidia/tegra124_car.c
--- a/sys/arch/arm/nvidia/tegra124_car.c Sun Apr 16 12:27:47 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra124_car.c Sun Apr 16 12:28:21 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra124_car.c,v 1.9 2017/04/14 09:50:56 jmcneill Exp $ */
+/* $NetBSD: tegra124_car.c,v 1.10 2017/04/16 12:28:21 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra124_car.c,v 1.9 2017/04/14 09:50:56 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra124_car.c,v 1.10 2017/04/16 12:28:21 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -626,8 +626,6 @@
CLK_GATE_H("fuse", "clk_m", CAR_DEV_H_FUSE),
CLK_GATE_U("soc_therm", "div_soc_therm", CAR_DEV_U_SOC_THERM),
CLK_GATE_V("tsensor", "div_tsensor", CAR_DEV_V_TSENSOR),
- CLK_GATE_SIMPLE("watchdog", "clk_m", CAR_RST_SOURCE_REG,
- CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN),
CLK_GATE_L("host1x", "div_host1x", CAR_DEV_L_HOST1X),
CLK_GATE_L("disp1", "mux_disp1", CAR_DEV_L_DISP1),
CLK_GATE_L("disp2", "mux_disp2", CAR_DEV_L_DISP2),
@@ -639,6 +637,22 @@
CLK_GATE_X("gpu", "pll_ref", CAR_DEV_X_GPU),
};
+struct tegra124_init_parent {
+ const char *clock;
+ const char *parent;
+} tegra124_init_parents[] = {
+ { "sata_oob", "pll_p_out0" },
+ { "sata", "pll_p_out0" },
+ { "hda", "pll_p_out0" },
+ { "hda2codec_2x", "pll_p_out0" },
+ { "soc_therm", "pll_p_out0" },
+ { "tsensor", "clk_m" },
+ { "xusb_host_src", "pll_p_out0" },
+ { "xusb_falcon_src", "pll_p_out0" },
+ { "xusb_ss_src", "pll_u_480" },
+ { "xusb_fs_src", "pll_u_48" },
+};
+
struct tegra124_car_rst {
u_int set_reg;
u_int clr_reg;
@@ -674,6 +688,8 @@
bus_space_tag_t sc_bst;
bus_space_handle_t sc_bsh;
+ struct clk_domain sc_clkdom;
+
u_int sc_clock_cells;
u_int sc_reset_cells;
@@ -684,6 +700,8 @@
static void tegra124_car_init(struct tegra124_car_softc *);
static void tegra124_car_utmip_init(struct tegra124_car_softc *);
static void tegra124_car_xusb_init(struct tegra124_car_softc *);
+static void tegra124_car_watchdog_init(struct tegra124_car_softc *);
+static void tegra124_car_parent_init(struct tegra124_car_softc *);
static void tegra124_car_rnd_attach(device_t);
static void tegra124_car_rnd_callback(size_t, void *);
@@ -715,7 +733,7 @@
const int phandle = faa->faa_phandle;
bus_addr_t addr;
bus_size_t size;
- int error;
+ int error, n;
if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
aprint_error(": couldn't get registers\n");
@@ -737,7 +755,10 @@
aprint_naive("\n");
aprint_normal(": CAR\n");
- clk_backend_register("tegra124", &tegra124_car_clock_funcs, sc);
+ sc->sc_clkdom.funcs = &tegra124_car_clock_funcs;
+ sc->sc_clkdom.priv = sc;
+ for (n = 0; n < __arraycount(tegra124_car_clocks); n++)
+ tegra124_car_clocks[n].base.domain = &sc->sc_clkdom;
fdtbus_register_clock_controller(self, phandle,
&tegra124_car_fdtclock_funcs);
@@ -752,8 +773,35 @@
static void
tegra124_car_init(struct tegra124_car_softc *sc)
{
+ tegra124_car_parent_init(sc);
tegra124_car_utmip_init(sc);
tegra124_car_xusb_init(sc);
+ tegra124_car_watchdog_init(sc);
+}
+
+static void
+tegra124_car_parent_init(struct tegra124_car_softc *sc)
+{
+ struct clk *clk, *clk_parent;
+ int error;
+ u_int n;
+
+ for (n = 0; n < __arraycount(tegra124_init_parents); n++) {
+ clk = clk_get(&sc->sc_clkdom, tegra124_init_parents[n].clock);
+ KASSERT(clk != NULL);
+ clk_parent = clk_get(&sc->sc_clkdom,
+ tegra124_init_parents[n].parent);
+ KASSERT(clk_parent != NULL);
+
+ error = clk_set_parent(clk, clk_parent);
+ if (error) {
+ aprint_error_dev(sc->sc_dev,
+ "couldn't set '%s' parent to '%s': %d\n",
+ clk->name, clk_parent->name, error);
+ }
+ clk_put(clk_parent);
+ clk_put(clk);
+ }
}
static void
@@ -835,6 +883,17 @@
}
static void
+tegra124_car_watchdog_init(struct tegra124_car_softc *sc)
+{
+ const bus_space_tag_t bst = sc->sc_bst;
+ const bus_space_handle_t bsh = sc->sc_bsh;
+
+ /* Enable watchdog timer reset for system */
+ tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG,
+ CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0);
+}
+
+static void
tegra124_car_rnd_attach(device_t self)
{
struct tegra124_car_softc * const sc = device_private(self);
diff -r 863662db4032 -r 9cc784ee6cd0 sys/arch/arm/nvidia/tegra_ahcisata.c
--- a/sys/arch/arm/nvidia/tegra_ahcisata.c Sun Apr 16 12:27:47 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra_ahcisata.c Sun Apr 16 12:28:21 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_ahcisata.c,v 1.9 2015/12/22 22:10:36 jmcneill Exp $ */
+/* $NetBSD: tegra_ahcisata.c,v 1.10 2017/04/16 12:28:21 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.9 2015/12/22 22:10:36 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.10 2017/04/16 12:28:21 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -284,26 +284,13 @@
tegra_ahcisata_init_clocks(struct tegra_ahcisata_softc *sc)
{
device_t self = sc->sc.sc_atac.atac_dev;
- struct clk *pll_p_out0;
int error;
- pll_p_out0 = clk_get("pll_p_out0");
- if (pll_p_out0 == NULL) {
- aprint_error_dev(self, "couldn't find pll_p_out0\n");
- return ENOENT;
- }
-
/* Assert resets */
fdtbus_reset_assert(sc->sc_rst_sata);
fdtbus_reset_assert(sc->sc_rst_sata_cold);
- /* Set SATA_OOB clock source to PLLP, 204MHz */
- error = clk_set_parent(sc->sc_clk_sata_oob, pll_p_out0);
- if (error) {
- aprint_error_dev(self, "couldn't set sata-oob parent: %d\n",
- error);
- return error;
- }
+ /* Set SATA_OOB clock source to 204MHz */
error = clk_set_rate(sc->sc_clk_sata_oob, 204000000);
if (error) {
aprint_error_dev(self, "couldn't set sata-oob rate: %d\n",
@@ -311,12 +298,7 @@
return error;
}
- /* Set SATA clock source to PLLP, 102MHz */
- error = clk_set_parent(sc->sc_clk_sata, pll_p_out0);
- if (error) {
- aprint_error_dev(self, "couldn't set sata parent: %d\n", error);
- return error;
- }
+ /* Set SATA clock source to 102MHz */
error = clk_set_rate(sc->sc_clk_sata, 102000000);
if (error) {
aprint_error_dev(self, "couldn't set sata rate: %d\n", error);
diff -r 863662db4032 -r 9cc784ee6cd0 sys/arch/arm/nvidia/tegra_drm.c
--- a/sys/arch/arm/nvidia/tegra_drm.c Sun Apr 16 12:27:47 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra_drm.c Sun Apr 16 12:28:21 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_drm.c,v 1.6 2016/01/30 00:00:56 riastradh Exp $ */
+/* $NetBSD: tegra_drm.c,v 1.7 2017/04/16 12:28:21 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_drm.c,v 1.6 2016/01/30 00:00:56 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_drm.c,v 1.7 2017/04/16 12:28:21 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -126,7 +126,6 @@
"hdmi-supply", "pll-supply", "vdd-supply"
};
struct fdtbus_regulator *reg;
- struct clk *pll_p_out0;
u_int n, ndc;
sc->sc_dev = self;
@@ -192,24 +191,7 @@
}
}
- pll_p_out0 = clk_get("pll_p_out0");
- if (pll_p_out0 == NULL) {
- aprint_error_dev(self, "couldn't get clock pll_p_out0\n");
- return;
- }
fdtbus_reset_assert(sc->sc_rst_host1x);
- error = clk_set_parent(sc->sc_clk_host1x, pll_p_out0);
- if (error) {
- aprint_error_dev(self, "couldn't set host1x clock parent: %d\n",
- error);
- return;
- }
- error = clk_set_rate(sc->sc_clk_host1x, 408000000);
- if (error) {
- aprint_error_dev(self, "couldn't set host1x frequency: %d\n",
- error);
- return;
- }
error = clk_enable(sc->sc_clk_host1x);
if (error) {
aprint_error_dev(self, "couldn't enable clock host1x: %d\n",
@@ -217,7 +199,6 @@
return;
}
fdtbus_reset_deassert(sc->sc_rst_host1x);
- clk_put(pll_p_out0);
prop_dictionary_get_bool(prop, "force-dvi", &sc->sc_force_dvi);
diff -r 863662db4032 -r 9cc784ee6cd0 sys/arch/arm/nvidia/tegra_hdaudio.c
--- a/sys/arch/arm/nvidia/tegra_hdaudio.c Sun Apr 16 12:27:47 2017 +0000
+++ b/sys/arch/arm/nvidia/tegra_hdaudio.c Sun Apr 16 12:28:21 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_hdaudio.c,v 1.7 2015/12/23 12:44:06 jmcneill Exp $ */
+/* $NetBSD: tegra_hdaudio.c,v 1.8 2017/04/16 12:28:21 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_hdaudio.c,v 1.7 2015/12/23 12:44:06 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_hdaudio.c,v 1.8 2017/04/16 12:28:21 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -183,26 +183,14 @@
tegra_hdaudio_init_clocks(struct tegra_hdaudio_softc *sc)
{
device_t self = sc->sc.sc_dev;
- struct clk *pll_p_out0;
int error;
- pll_p_out0 = clk_get("pll_p_out0");
- if (pll_p_out0 == NULL) {
- aprint_error_dev(self, "couldn't find pll_p_out0\n");
- return ENOENT;
- }
-
/* Assert resets */
fdtbus_reset_assert(sc->sc_rst_hda);
fdtbus_reset_assert(sc->sc_rst_hda2hdmi);
fdtbus_reset_assert(sc->sc_rst_hda2codec_2x);
/* Set hda to 48MHz and enable it */
- error = clk_set_parent(sc->sc_clk_hda, pll_p_out0);
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