[src/trunk]: src/sys/arch/arm/allwinner Use correct offset for PLL6 register.

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/0ec8d1e4ab90
branches:  trunk
changeset: 789804:0ec8d1e4ab90
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sun Sep 08 10:32:56 2013 +0000

description:
Use correct offset for PLL6 register.

diffstat:

 sys/arch/arm/allwinner/awin_board.c |  10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)

diffs (37 lines):

diff -r 95ecf8d7ccfe -r 0ec8d1e4ab90 sys/arch/arm/allwinner/awin_board.c
--- a/sys/arch/arm/allwinner/awin_board.c       Sun Sep 08 08:19:40 2013 +0000
+++ b/sys/arch/arm/allwinner/awin_board.c       Sun Sep 08 10:32:56 2013 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: awin_board.c,v 1.4 2013/09/07 02:09:23 matt Exp $      */
+/*     $NetBSD: awin_board.c,v 1.5 2013/09/08 10:32:56 jmcneill Exp $  */
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -34,7 +34,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.4 2013/09/07 02:09:23 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.5 2013/09/08 10:32:56 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -195,7 +195,8 @@
        /*
         * SATA needs PLL6 to be a 100MHz clock.
         */
-       const uint32_t ocfg = bus_space_read_4(bst, bsh, AWIN_PLL6_CFG_REG);
+       const uint32_t ocfg = bus_space_read_4(bst, bsh,
+           AWIN_CCM_OFFSET + AWIN_PLL6_CFG_REG);
        const u_int k = __SHIFTOUT(ocfg, AWIN_PLL_CFG_FACTOR_K);
 
        /*
@@ -208,6 +209,7 @@
        ncfg |= __SHIFTIN(25, AWIN_PLL_CFG_FACTOR_N);
        ncfg |= AWIN_PLL_CFG_ENABLE | AWIN_PLL6_CFG_SATA_CLK_EN;
        if (ncfg != ocfg) {
-               bus_space_write_4(bst, bsh, AWIN_PLL6_CFG_REG, ncfg);
+               bus_space_write_4(bst, bsh,
+                   AWIN_CCM_OFFSET + AWIN_PLL6_CFG_REG, ncfg);
        }
 }