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[src/trunk]: src/sys/arch Use dwc2 instead of octeon_usbc, and unify octeon_u...
details: https://anonhg.NetBSD.org/src/rev/82c3faf8039a
branches: trunk
changeset: 807994:82c3faf8039a
user: hikaru <hikaru%NetBSD.org@localhost>
date: Fri May 01 07:23:47 2015 +0000
description:
Use dwc2 instead of octeon_usbc, and unify octeon_usbn to new octeon_dwctwo.
Internal USB memory stick of EdgeRouter Lite works now.
diffstat:
sys/arch/evbmips/conf/ERLITE | 16 +-
sys/arch/mips/cavium/dev/octeon_dwctwo.c | 416 ++
sys/arch/mips/cavium/dev/octeon_usbc.c | 4627 ------------------------------
sys/arch/mips/cavium/dev/octeon_usbn.c | 438 --
sys/arch/mips/cavium/octeon1p_iobus.c | 6 +-
sys/arch/mips/conf/files.octeon | 8 +-
6 files changed, 432 insertions(+), 5079 deletions(-)
diffs (truncated from 5579 to 300 lines):
diff -r 87859b65bce8 -r 82c3faf8039a sys/arch/evbmips/conf/ERLITE
--- a/sys/arch/evbmips/conf/ERLITE Fri May 01 07:22:42 2015 +0000
+++ b/sys/arch/evbmips/conf/ERLITE Fri May 01 07:23:47 2015 +0000
@@ -1,11 +1,11 @@
-# $NetBSD: ERLITE,v 1.1 2015/04/29 08:32:00 hikaru Exp $
+# $NetBSD: ERLITE,v 1.2 2015/05/01 07:23:47 hikaru Exp $
include "arch/mips/conf/std.octeon"
include "arch/evbmips/conf/files.octeon"
#options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-#ident "ERLITE-$Revision: 1.1 $"
+#ident "ERLITE-$Revision: 1.2 $"
maxusers 32
@@ -131,11 +131,15 @@
octeon_gmx* at iobus?
cnmac* at octeon_gmx?
-#octeon_usbn* at iobus?
-#usb* at octeon_usbn?
+dwctwo* at iobus?
+usb* at dwctwo?
+
+uhub* at usb?
-#uhub* at usb?
-#ugen* at uhub? port ?
+# USB Mass Storage
+umass* at uhub? port ? configuration ? interface ?
+scsibus* at umass? channel ?
+sd* at scsibus? target ? lun ? # SCSI disk drives
atphy* at mii? phy ? # Attansic/Atheros PHYs
ukphy* at mii? phy ? # generic unknown PHYs
diff -r 87859b65bce8 -r 82c3faf8039a sys/arch/mips/cavium/dev/octeon_dwctwo.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/cavium/dev/octeon_dwctwo.c Fri May 01 07:23:47 2015 +0000
@@ -0,0 +1,416 @@
+/* $NetBSD: octeon_dwctwo.c,v 1.1 2015/05/01 07:23:47 hikaru Exp $ */
+
+/*
+ * Copyright (c) 2015 Masao Uebayashi <uebayasi%tombiinc.com@localhost>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Copyright (c) 2015 Internet Initiative Japan, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: octeon_dwctwo.c,v 1.1 2015/05/01 07:23:47 hikaru Exp $");
+
+#include "opt_octeon.h"
+#include "opt_usb.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/bus.h>
+#include <sys/workqueue.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+#include <dev/usb/usbdivar.h>
+#include <dev/usb/usb_mem.h>
+
+#include <mips/cavium/include/iobusvar.h>
+#include <mips/cavium/dev/octeon_ciureg.h>
+#include <mips/cavium/dev/octeon_usbnreg.h>
+#include <mips/cavium/dev/octeon_usbnvar.h>
+#include <mips/cavium/dev/octeon_usbcreg.h>
+#include <mips/cavium/dev/octeon_usbcvar.h>
+#include <mips/cavium/octeonvar.h>
+
+#include <dwc2/dwc2var.h>
+#include <dwc2/dwc2.h>
+#include "dwc2_core.h"
+
+struct octeon_dwc2_softc {
+ struct dwc2_softc sc_dwc2;
+ /* USBC bus space tag */
+ struct mips_bus_space sc_dwc2_bust;
+
+ /* USBN bus space */
+ bus_space_tag_t sc_bust;
+ bus_space_handle_t sc_regh;
+ bus_space_handle_t sc_reg2h;
+
+ void *sc_ih;
+};
+
+static int octeon_dwc2_match(device_t, struct cfdata *, void *);
+static void octeon_dwc2_attach(device_t, device_t, void *);
+static uint32_t octeon_dwc2_rd_4(void *, bus_space_handle_t,
+ bus_size_t);
+static void octeon_dwc2_wr_4(void *, bus_space_handle_t,
+ bus_size_t, uint32_t);
+int octeon_dwc2_set_dma_addr(device_t, bus_addr_t, int);
+static inline void octeon_dwc2_reg_assert(struct octeon_dwc2_softc *,
+ bus_size_t, uint64_t);
+static inline void octeon_dwc2_reg_deassert(struct octeon_dwc2_softc *,
+ bus_size_t, uint64_t);
+static inline uint64_t octeon_dwc2_reg_rd(struct octeon_dwc2_softc *,
+ bus_size_t);
+static inline void octeon_dwc2_reg_wr(struct octeon_dwc2_softc *,
+ bus_size_t, uint64_t);
+static inline void octeon_dwc2_reg2_assert(struct octeon_dwc2_softc *,
+ bus_size_t, uint64_t);
+static inline void octeon_dwc2_reg2_deassert(struct octeon_dwc2_softc *,
+ bus_size_t, uint64_t);
+static inline uint64_t octeon_dwc2_reg2_rd(struct octeon_dwc2_softc *,
+ bus_size_t);
+static inline void octeon_dwc2_reg2_wr(struct octeon_dwc2_softc *,
+ bus_size_t, uint64_t);
+
+static struct dwc2_core_params octeon_dwc2_params = {
+ .otg_cap = 2, /* 2 - No HNP/SRP capable */
+ .otg_ver = 0,
+ .dma_enable = 1,
+ .dma_desc_enable = 0,
+ .speed = 0, /* 0 - High Speed */
+ .enable_dynamic_fifo = 1,
+ .en_multiple_tx_fifo = 0,
+ .host_rx_fifo_size = 456,
+ .host_nperio_tx_fifo_size = 912,
+ .host_perio_tx_fifo_size = 256,
+ .max_transfer_size = 65535,
+ .max_packet_count = 511,
+ .host_channels = 8,
+ .phy_type = 1, /* UTMI */
+ .phy_utmi_width = 16, /* 16 bits */
+ .phy_ulpi_ddr = 0,
+ .phy_ulpi_ext_vbus = 0,
+ .i2c_enable = 0,
+ .ulpi_fs_ls = 0,
+ .host_support_fs_ls_low_power = 0,
+ .host_ls_low_power_phy_clk = 0, /* 48 MHz */
+ .ts_dline = 0,
+ .reload_ctl = 0,
+ .ahbcfg = 0, /* XXX */
+ .uframe_sched = 1,
+};
+
+CFATTACH_DECL_NEW(octeon_dwctwo, sizeof(struct octeon_dwc2_softc),
+ octeon_dwc2_match, octeon_dwc2_attach, NULL, NULL);
+
+static int
+octeon_dwc2_match(device_t parent, struct cfdata *cf, void *aux)
+{
+ struct iobus_attach_args *aa = aux;
+
+ if (strcmp(cf->cf_name, aa->aa_name) != 0)
+ return 0;
+
+ return 1;
+}
+
+static void
+octeon_dwc2_attach(device_t parent, device_t self, void *aux)
+{
+ struct octeon_dwc2_softc *sc = device_private(self);
+ struct iobus_attach_args *aa = aux;
+ uint64_t clk;
+ int status;
+
+ aprint_normal("\n");
+
+ sc->sc_dwc2.sc_dev = self;
+ sc->sc_bust = aa->aa_bust;
+
+ sc->sc_dwc2_bust.bs_cookie = sc;
+ sc->sc_dwc2_bust.bs_map = aa->aa_bust->bs_map;
+ sc->sc_dwc2_bust.bs_unmap = aa->aa_bust->bs_unmap;
+ sc->sc_dwc2_bust.bs_r_4 = octeon_dwc2_rd_4;
+ sc->sc_dwc2_bust.bs_w_4 = octeon_dwc2_wr_4;
+
+ sc->sc_dwc2.sc_iot = &sc->sc_dwc2_bust;
+ sc->sc_dwc2.sc_bus.dmatag = aa->aa_dmat;
+ sc->sc_dwc2.sc_params = &octeon_dwc2_params;
+ sc->sc_dwc2.sc_set_dma_addr = octeon_dwc2_set_dma_addr;
+
+ status = bus_space_map(sc->sc_dwc2.sc_iot, USBC_BASE, USBC_SIZE,
+ 0, &sc->sc_dwc2.sc_ioh);
+ if (status != 0)
+ panic("can't map USBC space");
+
+ status = bus_space_map(sc->sc_bust, USBN_BASE, USBN_SIZE,
+ 0, &sc->sc_regh);
+ if (status != 0)
+ panic("can't map USBN space");
+
+ status = bus_space_map(sc->sc_bust, USBN_2_BASE, USBN_2_SIZE,
+ 0, &sc->sc_reg2h);
+ if (status != 0)
+ panic("can't map USBN_2 space");
+
+ switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) {
+ case MIPS_CN50XX:
+ /*
+ * 2. Configure the reference clock, PHY, and HCLK:
+ * a. Write USBN_CLK_CTL[POR] = 1 and
+ * USBN_CLK_CTL[HRST,PRST,HCLK_RST] = 0
+ */
+ clk = octeon_dwc2_reg_rd(sc, USBN_CLK_CTL_OFFSET);
+ clk |= USBN_CLK_CTL_POR;
+ clk &= ~(USBN_CLK_CTL_HRST | USBN_CLK_CTL_PRST |
+ USBN_CLK_CTL_HCLK_RST | USBN_CLK_CTL_ENABLE);
+ /*
+ * b. Select the USB reference clock/crystal parameters by writing
+ * appropriate values to USBN_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON].
+ */
+ /* XXX board specific */
+ clk &= ~(USBN_CLK_CTL_P_C_SEL | USBN_CLK_CTL_P_RTYPE |
+ USBN_CLK_CTL_P_COM_ON);
+ /*
+ * c. Select the HCLK via writing USBN_CLK_CTL[DIVIDE, DIVIDE2] and
+ * setting USBN_CLK_CTL[ENABLE] = 1.
+ */
+ /* XXX board specific */
+ clk &= ~(USBN_CLK_CTL_DIVIDE | USBN_CLK_CTL_DIVIDE2);
+ clk |= SET_USBN_CLK_CTL_DIVIDE(0x4ULL)
+ | SET_USBN_CLK_CTL_DIVIDE2(0x0ULL);
+ octeon_dwc2_reg_wr(sc, USBN_CLK_CTL_OFFSET, clk);
+ /*
+ * d. Write USBN_CLK_CTL[HCLK_RST] = 1.
+ */
+ octeon_dwc2_reg_assert(sc, USBN_CLK_CTL_OFFSET, USBN_CLK_CTL_HCLK_RST);
+ /*
+ * e. Wait 64 core-clock cycles for HCLK to stabilize.
+ */
+ delay(1);
+ break;
+ case MIPS_CN31XX:
+ case MIPS_CN30XX:
+ /*
+ * 2. If changing the HCLK divide value:
+ * a. write USBN_CLK_CTL[DIVIDE] with the new divide value.
+ */
+ clk = octeon_dwc2_reg_rd(sc, USBN_CLK_CTL_OFFSET);
+ clk |= 0x4ULL & USBN_CLK_CTL_DIVIDE;
+ octeon_dwc2_reg_wr(sc, USBN_CLK_CTL_OFFSET, clk);
+ /*
+ * b. Wait 64 core-clock cycles for HCLK to stabilize.
+ */
+ delay(1);
+ break;
+ default:
+ panic("unknown H/W type"); /* XXX */
+ }
+
+ /*
+ * 3. Program the power-on reset field in the USBN clock-control register:
+ * USBN_CLK_CTL[POR] = 0
+ */
+ octeon_dwc2_reg_deassert(sc, USBN_CLK_CTL_OFFSET, USBN_CLK_CTL_POR);
+ /*
+ * 4. Wait 40 us for PHY clock to start (CN3xxx)
+ * 4. Wait 1 ms for PHY clock to start (CN50xx)
+ */
+ delay(1000);
+
+ /*
+ * 5. Program the Reset input from automatic test equipment field
+ * in the USBP control and status register:
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