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[src/trunk]: src/sys/dev/pci Add Downstream Port Containment (DPC) ECN and En...
details: https://anonhg.NetBSD.org/src/rev/f79d83aab9f8
branches: trunk
changeset: 823349:f79d83aab9f8
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Thu Apr 20 08:45:25 2017 +0000
description:
Add Downstream Port Containment (DPC) ECN and Enhanced DPC(eDPC) ECN.
diffstat:
sys/dev/pci/pci_subr.c | 146 +++++++++++++++++++++++++++++++++++++++++++++++-
sys/dev/pci/pcireg.h | 49 ++++++++++++++++-
2 files changed, 190 insertions(+), 5 deletions(-)
diffs (237 lines):
diff -r 612eef219d93 -r f79d83aab9f8 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c Thu Apr 20 08:45:09 2017 +0000
+++ b/sys/dev/pci/pci_subr.c Thu Apr 20 08:45:25 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.175 2017/04/20 05:48:38 msaitoh Exp $ */
+/* $NetBSD: pci_subr.c,v 1.176 2017/04/20 08:45:25 msaitoh Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.175 2017/04/20 05:48:38 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.176 2017/04/20 08:45:25 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -3525,7 +3525,145 @@
printf(" LNR Registration Limit: %u\n", num);
}
-/* XXX pci_conf_print_dpc_cap */
+static void
+pci_conf_print_dpc_pio(pcireg_t r)
+{
+ onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL);
+ onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL);
+ onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO);
+ onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL);
+ onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL);
+ onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO);
+ onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL);
+ onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL);
+ onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO);
+}
+
+static void
+pci_conf_print_dpc_cap(const pcireg_t *regs, int capoff, int extcapoff)
+{
+ pcireg_t reg, cap, ctl, stat, errsrc;
+ const char *trigstr;
+ bool rpext;
+
+ printf("\n Downstream Port Containment\n");
+
+ reg = regs[o2i(extcapoff + PCI_DPC_CCR)];
+ cap = reg & 0xffff;
+ ctl = reg >> 16;
+ rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false;
+ printf(" DPC Capability register: 0x%04x\n", cap);
+ printf(" DPC Interrupt Message Number: %02x\n",
+ (unsigned int)(cap & PCI_DPCCAP_IMSGN));
+ onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT);
+ onoff("Poisoned TLP Egress Blocking Supported", reg,
+ PCI_DPCCAP_POISONTLPEB);
+ onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG);
+ printf(" RP PIO Log Size: %u\n",
+ (unsigned int)__SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ));
+ onoff("DL_Active ERR_COR Signaling Supported", reg,
+ PCI_DPCCAP_DLACTECORS);
+ printf(" DPC Control register: 0x%04x\n", ctl);
+ switch (__SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) {
+ case 0:
+ trigstr = "disabled";
+ break;
+ case 1:
+ trigstr = "enabled(ERR_FATAL)";
+ break;
+ case 2:
+ trigstr = "enabled(ERR_NONFATAL or ERR_FATAL)";
+ break;
+ default:
+ trigstr = "(reserverd)";
+ break;
+ }
+ printf(" DPC Trigger Enable: %s\n", trigstr);
+ printf(" DPC Completion Control: %s Completion Status\n",
+ (reg & PCI_DPCCTL_COMPCTL)
+ ? "Unsupported Request(UR)" : "Completer Abort(CA)");
+ onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE);
+ onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN);
+ onoff("Poisoned TLP Egress Blocking Enable", reg,
+ PCI_DPCCTL_POISONTLPEB);
+ onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG);
+ onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR);
+
+ reg = regs[o2i(extcapoff + PCI_DPC_STATESID)];
+ stat = reg & 0xffff;
+ errsrc = reg >> 16;
+ printf(" DPC Status register: 0x%04x\n", stat);
+ onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT);
+ switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) {
+ case 0:
+ trigstr = "an unmasked uncorrectable error";
+ break;
+ case 1:
+ trigstr = "receiving an ERR_NONFATAL";
+ break;
+ case 2:
+ trigstr = "receiving an ERR_FATAL";
+ break;
+ case 3:
+ trigstr = "DPC Trigger Reason Extension field";
+ break;
+ }
+ printf(" DPC Trigger Reason: Due to %s\n", trigstr);
+ onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT);
+ if (rpext)
+ onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY);
+ switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) {
+ case 0:
+ trigstr = "Due to RP PIO error";
+ break;
+ case 1:
+ trigstr = "Due to the DPC Software trigger bit";
+ break;
+ default:
+ trigstr = "(reserved)";
+ break;
+ }
+ printf(" DPC Trigger Reason Extension: %s\n", trigstr);
+ if (rpext)
+ printf(" RP PIO First Error Pointer: %02x\n",
+ (unsigned int)__SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP));
+ printf(" DPC Error Source ID register: 0x%04x\n", errsrc);
+
+ if (!rpext)
+ return;
+ /*
+ * All of the following registers are implemented by a device which has
+ * RP Extensions for DPC
+ */
+
+ reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)];
+ printf(" RP PIO Status Register: 0x%04x\n", reg);
+ pci_conf_print_dpc_pio(reg);
+
+ reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)];
+ printf(" RP PIO Mask Register: 0x%04x\n", reg);
+ pci_conf_print_dpc_pio(reg);
+
+ reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)];
+ printf(" RP PIO Severity Register: 0x%04x\n", reg);
+ pci_conf_print_dpc_pio(reg);
+
+ reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)];
+ printf(" RP PIO SysError Register: 0x%04x\n", reg);
+ pci_conf_print_dpc_pio(reg);
+
+ reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)];
+ printf(" RP PIO Exception Register: 0x%04x\n", reg);
+ pci_conf_print_dpc_pio(reg);
+
+ printf(" RP PIO Header Log Register: start from 0x%03x\n",
+ extcapoff + PCI_DPC_RPPIO_HLOG);
+ printf(" RP PIO ImpSpec Log Register: start from 0x%03x\n",
+ extcapoff + PCI_DPC_RPPIO_IMPSLOG);
+ printf(" RP PIO TPL Prefix Log Register: start from 0x%03x\n",
+ extcapoff + PCI_DPC_RPPIO_TLPPLOG);
+}
+
static int
pci_conf_l1pm_cap_tposcale(unsigned char scale)
@@ -3714,7 +3852,7 @@
{ PCI_EXTCAP_LN_REQ, "LN Requester",
pci_conf_print_lnr_cap },
{ PCI_EXTCAP_DPC, "Downstream Port Containment",
- NULL },
+ pci_conf_print_dpc_cap },
{ PCI_EXTCAP_L1PM, "L1 PM Substates",
pci_conf_print_l1pm_cap },
{ PCI_EXTCAP_PTM, "Precision Time Management",
diff -r 612eef219d93 -r f79d83aab9f8 sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h Thu Apr 20 08:45:09 2017 +0000
+++ b/sys/dev/pci/pcireg.h Thu Apr 20 08:45:25 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.126 2017/04/17 09:33:00 msaitoh Exp $ */
+/* $NetBSD: pcireg.h,v 1.127 2017/04/20 08:45:25 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -1922,6 +1922,53 @@
* Downstream Port Containment
*/
+#define PCI_DPC_CCR 0x04 /* Capability and Control Register */
+#define PCI_DPCCAP_IMSGN __BITS(4, 0) /* Interrupt Message Number */
+#define PCI_DPCCAP_RPEXT __BIT(5) /* RP Extensions for DPC */
+#define PCI_DPCCAP_POISONTLPEB __BIT(6) /* Poisoned TLP Egress Blckng.*/
+#define PCI_DPCCAP_SWTRIG __BIT(7) /* DPC Software Triggering */
+#define PCI_DPCCAP_RPPIOLOGSZ __BITS(11, 8) /* RP PIO Log Size */
+#define PCI_DPCCAP_DLACTECORS __BIT(12) /* DL_Active ERR_COR Signaling*/
+#define PCI_DPCCTL_TIRGEN __BITS(17, 16) /* DPC Trigger Enable */
+#define PCI_DPCCTL_COMPCTL __BIT(18) /* DPC Completion Control */
+#define PCI_DPCCTL_IE __BIT(19) /* DPC Interrupt Enable */
+#define PCI_DPCCTL_ERRCOREN __BIT(20) /* DPC ERR_COR enable */
+#define PCI_DPCCTL_POISONTLPEB __BIT(21) /* Poisoned TLP Egress Blckng.*/
+#define PCI_DPCCTL_SWTRIG __BIT(22) /* DPC Software Trigger */
+#define PCI_DPCCTL_DLACTECOR __BIT(23) /* DL_Active ERR_COR Enable */
+
+#define PCI_DPC_STATESID 0x08 /* Status and Error Source ID Register */
+#define PCI_DPCSTAT_TSTAT __BIT(0) /* DPC Trigger Staus */
+#define PCI_DPCSTAT_TREASON __BITS(2, 1) /* DPC Trigger Reason */
+#define PCI_DPCSTAT_ISTAT __BIT(3) /* DPC Interrupt Status */
+#define PCI_DPCSTAT_RPBUSY __BIT(4) /* DPC RP Busy */
+#define PCI_DPCSTAT_TRIGREXT __BITS(6, 5) /* DPC Trigger Reason Extntn. */
+#define PCI_DPCSTAT_RPPIOFEP __BITS(12, 8) /* RP PIO First Error Pointer */
+#define PCI_DPCESID __BITS(31, 16) /* DPC Error Source ID */
+
+#define PCI_DPC_RPPIO_STAT 0x0c /* RP PIO Status Register */
+#define PCI_DPC_RPPIO_CFGUR_CPL __BIT(0) /* CfgReq received UR Complt. */
+#define PCI_DPC_RPPIO_CFGCA_CPL __BIT(1) /* CfgReq received CA Complt. */
+#define PCI_DPC_RPPIO_CFG_CTO __BIT(2) /* CfgReq Completion Timeout */
+#define PCI_DPC_RPPIO_IOUR_CPL __BIT(8) /* I/OReq received UR Complt. */
+#define PCI_DPC_RPPIO_IOCA_CPL __BIT(9) /* I/OReq received CA Complt. */
+#define PCI_DPC_RPPIO_IO_CTO __BIT(10) /* I/OReq Completion Timeout */
+#define PCI_DPC_RPPIO_MEMUR_CPL __BIT(16) /* MemReq received UR Complt. */
+#define PCI_DPC_RPPIO_MEMCA_CPL __BIT(17) /* MemReq received CA Complt. */
+#define PCI_DPC_RPPIO_MEM_CTO __BIT(18) /* MemReq Completion Timeout */
+
+#define PCI_DPC_RPPIO_MASK 0x10 /* RP PIO Mask Register */
+ /* Bits are the same as RP PIO Status Register */
+#define PCI_DPC_RPPIO_SEVE 0x14 /* RP PIO Severity Register */
+ /* Same */
+#define PCI_DPC_RPPIO_SYSERR 0x18 /* RP PIO SysError Register */
+ /* Same */
+#define PCI_DPC_RPPIO_EXCPT 0x1c /* RP PIO Exception Register */
+ /* Same */
+#define PCI_DPC_RPPIO_HLOG 0x20 /* RP PIO Header Log Register */
+#define PCI_DPC_RPPIO_IMPSLOG 0x30 /* RP PIO ImpSpec Log Register */
+#define PCI_DPC_RPPIO_TLPPLOG 0x34 /* RP PIO TPL Prefix Log Register */
+
/*
* Extended capability ID: 0x001e
* L1 PM Substates
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