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[src/trunk]: src/sys/arch/x86/include Add x2APIC register definitions.
details: https://anonhg.NetBSD.org/src/rev/18ea3b0c1848
branches: trunk
changeset: 823407:18ea3b0c1848
user: nonaka <nonaka%NetBSD.org@localhost>
date: Sat Apr 22 04:23:17 2017 +0000
description:
Add x2APIC register definitions.
diffstat:
sys/arch/x86/include/i82489reg.h | 59 +++++++++++++++++++++++---------------
sys/arch/x86/include/specialreg.h | 26 ++++++++++++++++-
2 files changed, 60 insertions(+), 25 deletions(-)
diffs (180 lines):
diff -r f429db8189bb -r 18ea3b0c1848 sys/arch/x86/include/i82489reg.h
--- a/sys/arch/x86/include/i82489reg.h Fri Apr 21 23:49:17 2017 +0000
+++ b/sys/arch/x86/include/i82489reg.h Sat Apr 22 04:23:17 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: i82489reg.h,v 1.13 2015/07/17 05:16:09 msaitoh Exp $ */
+/* $NetBSD: i82489reg.h,v 1.14 2017/04/22 04:23:17 nonaka Exp $ */
/*-
* Copyright (c) 1998, 2008 The NetBSD Foundation, Inc.
@@ -35,29 +35,30 @@
* "local" APIC.
*/
-#define LAPIC_ID 0x020 /* ID. RW */
+#define LAPIC_ID 0x020 /* ID. (xAPIC: RW, x2APIC: RO) */
# define LAPIC_ID_MASK 0xff000000
# define LAPIC_ID_SHIFT 24
-#define LAPIC_VERS 0x030 /* Version. R */
+#define LAPIC_VERS 0x030 /* Version. RO */
# define LAPIC_VERSION_MASK 0x000000ff
# define LAPIC_VERSION_LVT_MASK 0x00ff0000
# define LAPIC_VERSION_LVT_SHIFT 16
+# define LAPIC_VERSION_DIRECTED_EOI 0x01000000
#define LAPIC_TPRI 0x080 /* Task Prio. RW */
# define LAPIC_TPRI_MASK 0x000000ff
# define LAPIC_TPRI_INT_MASK 0x000000f0
# define LAPIC_TPRI_SUB_MASK 0x0000000f
-#define LAPIC_APRI 0x090 /* Arbitration prio R */
+#define LAPIC_APRI 0x090 /* Arbitration prio (xAPIC: RO, x2APIC: NA) */
# define LAPIC_APRI_MASK 0x000000ff
-#define LAPIC_PPRI 0x0a0 /* Processor prio. R */
+#define LAPIC_PPRI 0x0a0 /* Processor prio. RO */
#define LAPIC_EOI 0x0b0 /* End Int. W */
-#define LAPIC_RRR 0x0c0 /* Remote read R */
-#define LAPIC_LDR 0x0d0 /* Logical dest. RW */
+#define LAPIC_RRR 0x0c0 /* Remote read (xAPIC: RO, x2APIC: NA) */
+#define LAPIC_LDR 0x0d0 /* Logical dest. (xAPIC: RW, x2APIC: RO) */
-#define LAPIC_DFR 0x0e0 /* Dest. format RW */
+#define LAPIC_DFR 0x0e0 /* Dest. format (xAPIC: RW, x2APIC: NA) */
# define LAPIC_DFR_MASK 0xf0000000
# define LAPIC_DFR_FLAT 0xf0000000
# define LAPIC_DFR_CLUSTER 0x00000000
@@ -70,27 +71,30 @@
# define LAPIC_SVR_SWEN 0x00000100
# define LAPIC_SVR_FOCUS 0x00000200
# define LAPIC_SVR_FDIS 0x00000200
+# define LAPIC_SVR_EOI_BC_DIS 0x00001000
-#define LAPIC_ISR 0x100 /* In-Service Status */
-#define LAPIC_TMR 0x180 /* Trigger Mode */
-#define LAPIC_IRR 0x200 /* Interrupt Req */
-#define LAPIC_ESR 0x280 /* Err status. R */
+#define LAPIC_ISR 0x100 /* In-Service Status RO */
+#define LAPIC_TMR 0x180 /* Trigger Mode RO */
+#define LAPIC_IRR 0x200 /* Interrupt Req RO */
+#define LAPIC_ESR 0x280 /* Err status. RW */
-#define LAPIC_ICRLO 0x300 /* Int. cmd. RW */
-# define LAPIC_DLMODE_MASK 0x00000700
+#define LAPIC_LVT_CMCI 0x2f0 /* LVT CMCI RW */
+
+#define LAPIC_ICRLO 0x300 /* Int. cmd. (xAPIC: RW, x2APIC: RW64) */
+# define LAPIC_DLMODE_MASK 0x00000700 /* Delivery Mode */
# define LAPIC_DLMODE_FIXED 0x00000000
-# define LAPIC_DLMODE_LOW 0x00000100
+# define LAPIC_DLMODE_LOW 0x00000100 /* N/A in x2APIC mode */
# define LAPIC_DLMODE_SMI 0x00000200
# define LAPIC_DLMODE_NMI 0x00000400
# define LAPIC_DLMODE_INIT 0x00000500
# define LAPIC_DLMODE_STARTUP 0x00000600
-# define LAPIC_DLMODE_EXTINT 0x00000700
+# define LAPIC_DLMODE_EXTINT 0x00000700 /* N/A in x2APIC mode */
# define LAPIC_DSTMODE_PHYS 0x00000000
# define LAPIC_DSTMODE_LOG 0x00000800
-# define LAPIC_DLSTAT_BUSY 0x00001000
-# define LAPIC_DLSTAT_IDLE 0x00000000
+# define LAPIC_DLSTAT_BUSY 0x00001000 /* N/A in x2APIC mode */
+# define LAPIC_DLSTAT_IDLE 0x00000000 /* N/A in x2APIC mode */
# define LAPIC_LEVEL_MASK 0x00004000
# define LAPIC_LEVEL_ASSERT 0x00004000
@@ -106,8 +110,7 @@
# define LAPIC_DEST_ALLINCL 0x00080000
# define LAPIC_DEST_ALLEXCL 0x000c0000
-
-#define LAPIC_ICRHI 0x310 /* Int. cmd. RW */
+#define LAPIC_ICRHI 0x310 /* Int. cmd. (xAPIC: RW, x2APIC: NA) */
#define LAPIC_LVTT 0x320 /* Loc.vec.(timer) RW */
# define LAPIC_LVTT_VEC_MASK 0x000000ff
@@ -115,9 +118,15 @@
# define LAPIC_LVTT_M 0x00010000
# define LAPIC_LVTT_TM 0x00020000
-#define LAPIC_TMINT 0x330 /* Loc.vec (Thermal) */
-#define LAPIC_PCINT 0x340 /* Loc.vec (Perf Mon) */
+#define LAPIC_TMINT 0x330 /* Loc.vec (Thermal) RW */
+#define LAPIC_PCINT 0x340 /* Loc.vec (Perf Mon) RW */
#define LAPIC_LVINT0 0x350 /* Loc.vec (LINT0) RW */
+# define LAPIC_LVT_DM_MASK 0x00000700
+# define LAPIC_LVT_DM_FIXED 0x00000000
+# define LAPIC_LVT_DM_SMI 0x00000200
+# define LAPIC_LVT_DM_NMI 0x00000400
+# define LAPIC_LVT_DM_INIT 0x00000500
+# define LAPIC_LVT_DM_EXTINT 0x00000700
# define LAPIC_LVT_MASKED 0x00010000
# define LAPIC_LVT_LEVTRIG 0x00008000
# define LAPIC_LVT_REMOTE_IRR 0x00004000
@@ -129,7 +138,7 @@
#define LAPIC_ICR_TIMER 0x380 /* Initial count RW */
#define LAPIC_CCR_TIMER 0x390 /* Current count RO */
-#define LAPIC_DCR_TIMER 0x3e0 /* Divisor config register */
+#define LAPIC_DCR_TIMER 0x3e0 /* Divisor config RW */
# define LAPIC_DCRT_DIV1 0x0b
# define LAPIC_DCRT_DIV2 0x00
# define LAPIC_DCRT_DIV4 0x01
@@ -139,6 +148,9 @@
# define LAPIC_DCRT_DIV64 0x09
# define LAPIC_DCRT_DIV128 0x0a
+#define LAPIC_SELF_IPI 0x3f0 /* SELF IPI (xAPIC: NA, x2APIC: W) */
+# define LAPIC_SELF_IPI_VEC_MASK 0x000000ff
+
#define LAPIC_MSIADDR_BASE 0xfee00000
#define LAPIC_MSIADDR_DSTID_MASK __BITS(19, 12)
#define LAPIC_MSIADDR_RSVD0_MASK __BITS(11, 4)
@@ -220,4 +232,3 @@
# define LAPIC_MSR_ENABLE_x2 0x00000400 /* x2APIC mode */
# define LAPIC_MSR_ENABLE 0x00000800 /* software enable */
# define LAPIC_MSR_ADDR 0xfffff000 /* physical address */
-
diff -r f429db8189bb -r 18ea3b0c1848 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Fri Apr 21 23:49:17 2017 +0000
+++ b/sys/arch/x86/include/specialreg.h Sat Apr 22 04:23:17 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.95 2017/03/11 10:33:46 maxv Exp $ */
+/* $NetBSD: specialreg.h,v 1.96 2017/04/22 04:23:17 nonaka Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -660,6 +660,30 @@
#define MSR_MC4_ADDR 0x412
#define MSR_MC4_MISC 0x413
/* 0x480 - 0x490 VMX */
+#define MSR_X2APIC_BASE 0x800 /* 0x800 - 0xBFF */
+#define MSR_X2APIC_ID 0x002 /* x2APIC ID. (RO) */
+#define MSR_X2APIC_VERS 0x003 /* Version. (RO) */
+#define MSR_X2APIC_TPRI 0x008 /* Task Prio. (RW) */
+#define MSR_X2APIC_PPRI 0x00a /* Processor prio. (RO) */
+#define MSR_X2APIC_EOI 0x00b /* End Int. (W) */
+#define MSR_X2APIC_LDR 0x00d /* Logical dest. (RO) */
+#define MSR_X2APIC_SVR 0x00f /* Spurious intvec (RW) */
+#define MSR_X2APIC_ISR 0x010 /* In-Service Status (RO) */
+#define MSR_X2APIC_TMR 0x018 /* Trigger Mode (RO) */
+#define MSR_X2APIC_IRR 0x020 /* Interrupt Req (RO) */
+#define MSR_X2APIC_ESR 0x028 /* Err status. (RW) */
+#define MSR_X2APIC_LVT_CMCI 0x02f /* LVT CMCI (RW) */
+#define MSR_X2APIC_ICRLO 0x030 /* Int. cmd. (RW64) */
+#define MSR_X2APIC_LVTT 0x032 /* Loc.vec.(timer) (RW) */
+#define MSR_X2APIC_TMINT 0x033 /* Loc.vec (Thermal) (RW) */
+#define MSR_X2APIC_PCINT 0x034 /* Loc.vec (Perf Mon) (RW) */
+#define MSR_X2APIC_LVINT0 0x035 /* Loc.vec (LINT0) (RW) */
+#define MSR_X2APIC_LVINT1 0x036 /* Loc.vec (LINT1) (RW) */
+#define MSR_X2APIC_LVERR 0x037 /* Loc.vec (ERROR) (RW) */
+#define MSR_X2APIC_ICR_TIMER 0x038 /* Initial count (RW) */
+#define MSR_X2APIC_CCR_TIMER 0x039 /* Current count (RO) */
+#define MSR_X2APIC_DCR_TIMER 0x03e /* Divisor config (RW) */
+#define MSR_X2APIC_SELF_IPI 0x03f /* SELF IPI (W) */
/*
* VIA "Nehemiah" MSRs
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