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[src/trunk]: src/sys/external/bsd/dwc2 Adapt the Synopsys DWC2 driver to NetBSD.
details: https://anonhg.NetBSD.org/src/rev/a560d4edb0c3
branches: trunk
changeset: 789736:a560d4edb0c3
user: skrll <skrll%NetBSD.org@localhost>
date: Thu Sep 05 20:25:27 2013 +0000
description:
Adapt the Synopsys DWC2 driver to NetBSD.
Still work-in-progress
diffstat:
sys/external/bsd/dwc2/conf/files.dwc2 | 17 +
sys/external/bsd/dwc2/dist/dwc2_core.c | 474 +++---
sys/external/bsd/dwc2/dist/dwc2_core.h | 39 +-
sys/external/bsd/dwc2/dist/dwc2_coreintr.c | 116 +-
sys/external/bsd/dwc2/dist/dwc2_hcd.c | 1168 +++--------------
sys/external/bsd/dwc2/dist/dwc2_hcd.h | 85 +-
sys/external/bsd/dwc2/dist/dwc2_hcdddma.c | 102 +-
sys/external/bsd/dwc2/dist/dwc2_hcdintr.c | 176 +-
sys/external/bsd/dwc2/dist/dwc2_hcdqueue.c | 134 +-
sys/external/bsd/dwc2/dwc2.c | 1736 ++++++++++++++++++++++++++++
sys/external/bsd/dwc2/dwc2.h | 227 +++
sys/external/bsd/dwc2/dwc2var.h | 136 ++
sys/external/bsd/dwc2/dwctwo2netbsd | 118 +
13 files changed, 3103 insertions(+), 1425 deletions(-)
diffs (truncated from 6860 to 300 lines):
diff -r 2f24c131ae25 -r a560d4edb0c3 sys/external/bsd/dwc2/conf/files.dwc2
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/external/bsd/dwc2/conf/files.dwc2 Thu Sep 05 20:25:27 2013 +0000
@@ -0,0 +1,17 @@
+# $NetBSD: files.dwc2,v 1.1 2013/09/05 20:25:27 skrll Exp $
+
+# DesignWare HS OTG Controller
+#
+device dwctwo: usbus, usbroothub, usb_dma
+file external/bsd/dwc2/dwc2.c dwctwo needs-flag
+
+defflag opt_usb.h DWC2_DEBUG
+
+makeoptions dwctwo CPPFLAGS+=" -I$S/external/bsd/common/include -I$S/external/bsd -I$S/external/bsd/dwc2/dist"
+
+file external/bsd/dwc2/dist/dwc2_core.c dwctwo
+file external/bsd/dwc2/dist/dwc2_coreintr.c dwctwo
+file external/bsd/dwc2/dist/dwc2_hcd.c dwctwo
+file external/bsd/dwc2/dist/dwc2_hcdddma.c dwctwo
+file external/bsd/dwc2/dist/dwc2_hcdintr.c dwctwo
+file external/bsd/dwc2/dist/dwc2_hcdqueue.c dwctwo
diff -r 2f24c131ae25 -r a560d4edb0c3 sys/external/bsd/dwc2/dist/dwc2_core.c
--- a/sys/external/bsd/dwc2/dist/dwc2_core.c Thu Sep 05 17:35:11 2013 +0000
+++ b/sys/external/bsd/dwc2/dist/dwc2_core.c Thu Sep 05 20:25:27 2013 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc2_core.c,v 1.1.1.1 2013/09/05 07:53:10 skrll Exp $ */
+/* $NetBSD: dwc2_core.c,v 1.2 2013/09/05 20:25:27 skrll Exp $ */
/*
* core.c - DesignWare HS OTG Controller common routines
@@ -41,22 +41,31 @@
* DWC_otg hardware. These services are used by both the Host Controller
* Driver and the Peripheral Controller Driver.
*/
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: dwc2_core.c,v 1.2 2013/09/05 20:25:27 skrll Exp $");
+
+#include <sys/types.h>
+#include <sys/bus.h>
+#include <sys/proc.h>
+#include <sys/callout.h>
+#include <sys/mutex.h>
+#include <sys/pool.h>
+#include <sys/workqueue.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+#include <dev/usb/usbdivar.h>
+#include <dev/usb/usb_mem.h>
+
#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/dma-mapping.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/usb.h>
+#include <linux/list.h>
-#include <linux/usb/hcd.h>
-#include <linux/usb/ch11.h>
+#include <dwc2/dwc2.h>
+#include <dwc2/dwc2var.h>
-#include "core.h"
-#include "hcd.h"
+#include "dwc2_core.h"
+#include "dwc2_hcd.h"
/**
* dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
@@ -69,10 +78,10 @@
u32 intmsk;
/* Clear any pending OTG Interrupts */
- writel(0xffffffff, hsotg->regs + GOTGINT);
+ DWC2_WRITE_4(hsotg, GOTGINT, 0xffffffff);
/* Clear any pending interrupts */
- writel(0xffffffff, hsotg->regs + GINTSTS);
+ DWC2_WRITE_4(hsotg, GINTSTS, 0xffffffff);
/* Enable the interrupts in the GINTMSK */
intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
@@ -83,7 +92,7 @@
intmsk |= GINTSTS_CONIDSTSCHNG | GINTSTS_WKUPINT | GINTSTS_USBSUSP |
GINTSTS_SESSREQINT;
- writel(intmsk, hsotg->regs + GINTMSK);
+ DWC2_WRITE_4(hsotg, GINTMSK, intmsk);
}
/*
@@ -108,10 +117,10 @@
}
dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
- hcfg = readl(hsotg->regs + HCFG);
+ hcfg = DWC2_READ_4(hsotg, HCFG);
hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
hcfg |= val;
- writel(hcfg, hsotg->regs + HCFG);
+ DWC2_WRITE_4(hsotg, HCFG, hcfg);
}
/*
@@ -128,7 +137,7 @@
/* Wait for AHB master IDLE state */
do {
usleep_range(20000, 40000);
- greset = readl(hsotg->regs + GRSTCTL);
+ greset = DWC2_READ_4(hsotg, GRSTCTL);
if (++count > 50) {
dev_warn(hsotg->dev,
"%s() HANG! AHB Idle GRSTCTL=%0x\n",
@@ -140,10 +149,10 @@
/* Core Soft Reset */
count = 0;
greset |= GRSTCTL_CSFTRST;
- writel(greset, hsotg->regs + GRSTCTL);
+ DWC2_WRITE_4(hsotg, GRSTCTL, greset);
do {
usleep_range(20000, 40000);
- greset = readl(hsotg->regs + GRSTCTL);
+ greset = DWC2_READ_4(hsotg, GRSTCTL);
if (++count > 50) {
dev_warn(hsotg->dev,
"%s() HANG! Soft Reset GRSTCTL=%0x\n",
@@ -169,9 +178,9 @@
*/
if (select_phy) {
dev_dbg(hsotg->dev, "FS PHY selected\n");
- usbcfg = readl(hsotg->regs + GUSBCFG);
+ usbcfg = DWC2_READ_4(hsotg, GUSBCFG);
usbcfg |= GUSBCFG_PHYSEL;
- writel(usbcfg, hsotg->regs + GUSBCFG);
+ DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg);
/* Reset after a PHY select */
dwc2_core_reset(hsotg);
@@ -189,18 +198,18 @@
dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
/* Program GUSBCFG.OtgUtmiFsSel to I2C */
- usbcfg = readl(hsotg->regs + GUSBCFG);
+ usbcfg = DWC2_READ_4(hsotg, GUSBCFG);
usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
- writel(usbcfg, hsotg->regs + GUSBCFG);
+ DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg);
/* Program GI2CCTL.I2CEn */
- i2cctl = readl(hsotg->regs + GI2CCTL);
+ i2cctl = DWC2_READ_4(hsotg, GI2CCTL);
i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
i2cctl &= ~GI2CCTL_I2CEN;
- writel(i2cctl, hsotg->regs + GI2CCTL);
+ DWC2_WRITE_4(hsotg, GI2CCTL, i2cctl);
i2cctl |= GI2CCTL_I2CEN;
- writel(i2cctl, hsotg->regs + GI2CCTL);
+ DWC2_WRITE_4(hsotg, GI2CCTL, i2cctl);
}
}
@@ -211,7 +220,7 @@
if (!select_phy)
return;
- usbcfg = readl(hsotg->regs + GUSBCFG);
+ usbcfg = DWC2_READ_4(hsotg, GUSBCFG);
/*
* HS PHY parameters. These parameters are preserved during soft reset
@@ -239,7 +248,7 @@
break;
}
- writel(usbcfg, hsotg->regs + GUSBCFG);
+ DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg);
/* Reset after setting the PHY parameters */
dwc2_core_reset(hsotg);
@@ -265,21 +274,21 @@
fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
hsotg->core_params->ulpi_fs_ls > 0) {
dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
- usbcfg = readl(hsotg->regs + GUSBCFG);
+ usbcfg = DWC2_READ_4(hsotg, GUSBCFG);
usbcfg |= GUSBCFG_ULPI_FS_LS;
usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
- writel(usbcfg, hsotg->regs + GUSBCFG);
+ DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg);
} else {
- usbcfg = readl(hsotg->regs + GUSBCFG);
+ usbcfg = DWC2_READ_4(hsotg, GUSBCFG);
usbcfg &= ~GUSBCFG_ULPI_FS_LS;
usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
- writel(usbcfg, hsotg->regs + GUSBCFG);
+ DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg);
}
}
static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
{
- u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
+ u32 ahbcfg = DWC2_READ_4(hsotg, GAHBCFG);
switch (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) {
case GHWCFG2_EXT_DMA_ARCH:
@@ -318,7 +327,7 @@
if (hsotg->core_params->dma_enable > 0)
ahbcfg |= GAHBCFG_DMA_EN;
- writel(ahbcfg, hsotg->regs + GAHBCFG);
+ DWC2_WRITE_4(hsotg, GAHBCFG, ahbcfg);
return 0;
}
@@ -327,7 +336,7 @@
{
u32 usbcfg;
- usbcfg = readl(hsotg->regs + GUSBCFG);
+ usbcfg = DWC2_READ_4(hsotg, GUSBCFG);
usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
switch (hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) {
@@ -355,7 +364,7 @@
break;
}
- writel(usbcfg, hsotg->regs + GUSBCFG);
+ DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg);
}
/**
@@ -366,14 +375,14 @@
* @select_phy: If true then also set the Phy type
* @irq: If >= 0, the irq to register
*/
-int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq)
+int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy)
{
u32 usbcfg, otgctl;
int retval;
dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
- usbcfg = readl(hsotg->regs + GUSBCFG);
+ usbcfg = DWC2_READ_4(hsotg, GUSBCFG);
/* Set ULPI External VBUS bit if needed */
usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
@@ -386,7 +395,7 @@
if (hsotg->core_params->ts_dline > 0)
usbcfg |= GUSBCFG_TERMSELDLPULSE;
- writel(usbcfg, hsotg->regs + GUSBCFG);
+ DWC2_WRITE_4(hsotg, GUSBCFG, usbcfg);
/* Reset the Controller */
dwc2_core_reset(hsotg);
@@ -398,9 +407,9 @@
hsotg->total_fifo_size = hsotg->hwcfg3 >> GHWCFG3_DFIFO_DEPTH_SHIFT &
GHWCFG3_DFIFO_DEPTH_MASK >> GHWCFG3_DFIFO_DEPTH_SHIFT;
- hsotg->rx_fifo_size = readl(hsotg->regs + GRXFSIZ);
+ hsotg->rx_fifo_size = DWC2_READ_4(hsotg, GRXFSIZ);
hsotg->nperio_tx_fifo_size =
- readl(hsotg->regs + GNPTXFSIZ) >> 16 & 0xffff;
+ DWC2_READ_4(hsotg, GNPTXFSIZ) >> 16 & 0xffff;
dev_dbg(hsotg->dev, "Total FIFO SZ=%d\n", hsotg->total_fifo_size);
dev_dbg(hsotg->dev, "RxFIFO SZ=%d\n", hsotg->rx_fifo_size);
@@ -420,26 +429,16 @@
dwc2_gusbcfg_init(hsotg);
/* Program the GOTGCTL register */
- otgctl = readl(hsotg->regs + GOTGCTL);
+ otgctl = DWC2_READ_4(hsotg, GOTGCTL);
otgctl &= ~GOTGCTL_OTGVER;
if (hsotg->core_params->otg_ver > 0)
otgctl |= GOTGCTL_OTGVER;
- writel(otgctl, hsotg->regs + GOTGCTL);
+ DWC2_WRITE_4(hsotg, GOTGCTL, otgctl);
dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);
/* Clear the SRP success bit for FS-I2c */
hsotg->srp_success = 0;
- if (irq >= 0) {
- dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
- irq);
- retval = devm_request_irq(hsotg->dev, irq,
- dwc2_handle_common_intr, IRQF_SHARED,
- dev_name(hsotg->dev), hsotg);
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