[src/trunk]: src/sys/arch/arm/allwinner Add AWIN_AHCI_DMA

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/742b1c1ee4de
branches:  trunk
changeset: 789828:742b1c1ee4de
user:      matt <matt%NetBSD.org@localhost>
date:      Mon Sep 09 17:52:48 2013 +0000

description:
Add AWIN_AHCI_DMA
Do a little cleanup

diffstat:

 sys/arch/arm/allwinner/awin_reg.h |  18 ++++++++++++------
 1 files changed, 12 insertions(+), 6 deletions(-)

diffs (41 lines):

diff -r 48cb8e1e37b5 -r 742b1c1ee4de sys/arch/arm/allwinner/awin_reg.h
--- a/sys/arch/arm/allwinner/awin_reg.h Mon Sep 09 15:04:12 2013 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Mon Sep 09 17:52:48 2013 +0000
@@ -371,7 +371,8 @@
 #define AWIN_EMAC_SAFX3_L_REG          0x00BC
 #define AWIN_EMAC_SAFX3_H_REG          0x00C0
 
-#define AWIN_ACHI_BISTAFR_REG          0x00A0
+#define AWIN_AHCI_DMA_REG              0x0070
+#define AWIN_AHCI_BISTAFR_REG          0x00A0
 #define AWIN_AHCI_BISTCR_REG           0x00A4
 #define AWIN_AHCI_BISTFCTR_REG         0x00A8
 #define AWIN_AHCI_BISTSR_REG           0x00AC
@@ -471,17 +472,22 @@
 
 #define AWIN_PLL_CFG_ENABLE            __BIT(31)
 #define AWIN_PLL_CFG_BYPASS            __BIT(30)
-#define AWIN_PLL5_CFG_DDR_CLK_EN       __BIT(29)
 #define AWIN_PLL_CFG_EXG_MODE          __BIT(25)
 #define AWIN_PLL_CFG_OUT_EXP_DIVP      __BITS(17,16)
-#define AWIN_PLL6_CFG_SATA_CLK_EN      __BIT(14)
 #define AWIN_PLL_CFG_FACTOR_N          __BITS(12,8)
-#define AWIN_PLL5_CFG_LDO_EN           __BIT(7)
 #define AWIN_PLL_CFG_FACTOR_K          __BITS(5,4)
-#define AWIN_PLL5_CFG_FACTOR_M1                __BITS(3,2)
+#define AWIN_PLL_CFG_FACTOR_M          __BITS(1,0)
+
 #define AWIN_PLL1_SIG_DELT_PAT_IN      __BIT(3)
 #define AWIN_PLL1_SIG_DELT_PAT_EN      __BIT(2)
-#define AWIN_PLL_CFG_FACTOR_M          __BITS(1,0)
+
+#define AWIN_PLL5_CFG_DDR_CLK_EN       __BIT(29)
+#define AWIN_PLL5_CFG_LDO_EN           __BIT(7)
+#define AWIN_PLL5_CFG_FACTOR_M1                __BITS(3,2)
+
+#define AWIN_PLL6_VCO_BIAS             __BITS(29,25)
+#define AWIN_PLL6_PLL_BIAS             __BITS(24,20)
+#define AWIN_PLL6_CFG_SATA_CLK_EN      __BIT(14)
 
 #define AWIN_CPU_CLK_SRC_SEL           __BITS(17,16)
 #define AWIN_CPU_CLK_SRC_SEL_LOSC      0