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[src/trunk]: src/sys/arch Add SMP support to VEXPRESS_A15 kernel. Enable with...
details: https://anonhg.NetBSD.org/src/rev/bb7ba682af12
branches: trunk
changeset: 824362:bb7ba682af12
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Fri Jun 02 20:16:05 2017 +0000
description:
Add SMP support to VEXPRESS_A15 kernel. Enable with '-smp 2' on qemu
command line.
diffstat:
sys/arch/arm/vexpress/vexpress_platform.c | 59 +++++++++++++++++++++++++++---
sys/arch/arm/vexpress/vexpress_platform.h | 40 +++++++++++++++++++++
sys/arch/evbarm/conf/VEXPRESS_A15 | 5 +-
sys/arch/evbarm/vexpress/vexpress_start.S | 23 +++++++++--
4 files changed, 113 insertions(+), 14 deletions(-)
diffs (217 lines):
diff -r 6191eec7d4ea -r bb7ba682af12 sys/arch/arm/vexpress/vexpress_platform.c
--- a/sys/arch/arm/vexpress/vexpress_platform.c Fri Jun 02 19:58:31 2017 +0000
+++ b/sys/arch/arm/vexpress/vexpress_platform.c Fri Jun 02 20:16:05 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: vexpress_platform.c,v 1.1 2017/06/02 15:22:47 jmcneill Exp $ */
+/* $NetBSD: vexpress_platform.c,v 1.2 2017/06/02 20:16:05 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -30,7 +30,7 @@
#include "opt_fdt_arm.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: vexpress_platform.c,v 1.1 2017/06/02 15:22:47 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: vexpress_platform.c,v 1.2 2017/06/02 20:16:05 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -49,14 +49,14 @@
#include <arm/cortex/gtmr_var.h>
+#include <arm/cortex/gic_reg.h>
+
#include <evbarm/dev/plcomvar.h>
+#include <arm/vexpress/vexpress_platform.h>
+
#define VEXPRESS_REF_FREQ 24000000
-#define VEXPRESS_CORE_VBASE 0xf0000000
-#define VEXPRESS_CORE_PBASE 0x10000000
-#define VEXPRESS_CORE_SIZE 0x10000000
-
#define DEVMAP_ALIGN(a) ((a) & ~L1_S_OFFSET)
#define DEVMAP_SIZE(s) roundup2((s), L1_S_SIZE)
#define DEVMAP_ENTRY(va, pa, sz) \
@@ -100,6 +100,46 @@
bus_space_write_4(sysreg_bst, sysreg_bsh, (o), (v))
+static void
+vexpress_a15_smp_init(void)
+{
+ extern void cortex_mpstart(void);
+ bus_space_tag_t gicd_bst = &armv7_generic_bs_tag;
+ bus_space_handle_t gicd_bsh;
+ int started = 0;
+
+ /* Bitmask of CPUs (non-BSP) to start */
+ for (int i = 1; i < arm_cpu_max; i++)
+ started |= __BIT(i);
+
+ /* Write init vec to SYS_FLAGS register */
+ SYSREG_WRITE(SYS_FLAGSCLR, 0xffffffff);
+ SYSREG_WRITE(SYS_FLAGS, (uint32_t)cortex_mpstart);
+
+ /* Map GIC distributor */
+ bus_space_map(gicd_bst, VEXPRESS_GIC_PBASE + GICD_BASE,
+ 0x1000, 0, &gicd_bsh);
+
+ /* Enable GIC distributor */
+ bus_space_write_4(gicd_bst, gicd_bsh,
+ GICD_CTRL, GICD_CTRL_Enable);
+
+ /* Send sw interrupt to APs */
+ const uint32_t sgir = GICD_SGIR_TargetListFilter_NotMe;
+ bus_space_write_4(gicd_bst, gicd_bsh, GICD_SGIR, sgir);
+
+ /* Wait for APs to start */
+ for (u_int i = 0x10000000; i > 0; i--) {
+ arm_dmb();
+ if (arm_cpu_hatched == started)
+ break;
+ }
+
+ /* Disable GIC distributor */
+ bus_space_write_4(gicd_bst, gicd_bsh, GICD_CTRL, 0);
+}
+
+
static const struct pmap_devmap *
vexpress_platform_devmap(void)
{
@@ -107,6 +147,9 @@
DEVMAP_ENTRY(VEXPRESS_CORE_VBASE,
VEXPRESS_CORE_PBASE,
VEXPRESS_CORE_SIZE),
+ DEVMAP_ENTRY(VEXPRESS_GIC_VBASE,
+ VEXPRESS_GIC_PBASE,
+ VEXPRESS_GIC_SIZE),
DEVMAP_ENTRY_END
};
@@ -118,6 +161,10 @@
{
bus_space_map(sysreg_bst, SYSREG_BASE, SYSREG_SIZE, 0,
&sysreg_bsh);
+
+ arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
+
+ vexpress_a15_smp_init();
}
static void
diff -r 6191eec7d4ea -r bb7ba682af12 sys/arch/arm/vexpress/vexpress_platform.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/vexpress/vexpress_platform.h Fri Jun 02 20:16:05 2017 +0000
@@ -0,0 +1,40 @@
+/* $NetBSD: vexpress_platform.h,v 1.1 2017/06/02 20:16:05 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARM_VEXPRESS_PLATFORM_H
+#define _ARM_VEXPRESS_PLATFORM_H
+
+#define VEXPRESS_CORE_VBASE 0xf0000000
+#define VEXPRESS_CORE_PBASE 0x10000000
+#define VEXPRESS_CORE_SIZE 0x0ff00000
+
+#define VEXPRESS_GIC_VBASE (VEXPRESS_CORE_VBASE + VEXPRESS_CORE_SIZE)
+#define VEXPRESS_GIC_PBASE 0x2c000000
+#define VEXPRESS_GIC_SIZE 0x00100000
+
+#endif /* _ARM_VEXPRESS_PLATFORM_H */
diff -r 6191eec7d4ea -r bb7ba682af12 sys/arch/evbarm/conf/VEXPRESS_A15
--- a/sys/arch/evbarm/conf/VEXPRESS_A15 Fri Jun 02 19:58:31 2017 +0000
+++ b/sys/arch/evbarm/conf/VEXPRESS_A15 Fri Jun 02 20:16:05 2017 +0000
@@ -1,5 +1,5 @@
#
-# $NetBSD: VEXPRESS_A15,v 1.8 2017/06/02 15:22:47 jmcneill Exp $
+# $NetBSD: VEXPRESS_A15,v 1.9 2017/06/02 20:16:05 jmcneill Exp $
#
# ARM Versatile Express A15
#
@@ -8,8 +8,7 @@
include "arch/evbarm/conf/GENERIC.common"
options CPU_CORTEXA15
-options SOC_TEGRA124
-#options MULTIPROCESSOR
+options MULTIPROCESSOR
pseudo-device openfirm # /dev/openfirm
diff -r 6191eec7d4ea -r bb7ba682af12 sys/arch/evbarm/vexpress/vexpress_start.S
--- a/sys/arch/evbarm/vexpress/vexpress_start.S Fri Jun 02 19:58:31 2017 +0000
+++ b/sys/arch/evbarm/vexpress/vexpress_start.S Fri Jun 02 20:16:05 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: vexpress_start.S,v 1.3 2017/06/02 15:22:47 jmcneill Exp $ */
+/* $NetBSD: vexpress_start.S,v 1.4 2017/06/02 20:16:05 jmcneill Exp $ */
/*-
* Copyright (c) 2015 The NetBSD Foundation, Inc.
@@ -38,14 +38,17 @@
#include <arm/armreg.h>
#include "assym.h"
-#define VEXPRESS_CORE_VBASE 0xf0000000
-#define VEXPRESS_CORE_PBASE 0x10000000
-#define VEXPRESS_CORE_SIZE 0x10000000
+#include <arm/vexpress/vexpress_platform.h>
-RCSID("$NetBSD: vexpress_start.S,v 1.3 2017/06/02 15:22:47 jmcneill Exp $")
+RCSID("$NetBSD: vexpress_start.S,v 1.4 2017/06/02 20:16:05 jmcneill Exp $")
+#ifdef VERBOSE_INIT_ARM
#define XPUTC(n) mov r0, n; bl xputc
#define XPUTC2(n) mov r0, n; blx r11
+#else
+#define XPUTC(n)
+#define XPUTC2(n)
+#endif
#define INIT_MEMSIZE 128
#define TEMP_L1_TABLE (KERNEL_BASE - KERNEL_BASE_VOFFSET + INIT_MEMSIZE * L1_S_SIZE - L1_TABLE_SIZE)
@@ -141,6 +144,16 @@
VEXPRESS_CORE_SIZE / L1_S_SIZE,
L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
+ /* Map VEXPRESS GIC */
+ MMU_INIT(VEXPRESS_GIC_VBASE, VEXPRESS_GIC_PBASE,
+ VEXPRESS_GIC_SIZE / L1_S_SIZE,
+ L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
+
+ /* Map VEXPRESS GIC */
+ MMU_INIT(VEXPRESS_GIC_PBASE, VEXPRESS_GIC_PBASE,
+ VEXPRESS_GIC_SIZE / L1_S_SIZE,
+ L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
+
/* end of table */
MMU_INIT(0, 0, 0, 0)
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