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[src/trunk]: src/sys/arch Provide and use some CP0 accessor functions instead...
details: https://anonhg.NetBSD.org/src/rev/4e93e176eff8
branches: trunk
changeset: 824054:4e93e176eff8
user: skrll <skrll%NetBSD.org@localhost>
date: Sun May 21 06:49:12 2017 +0000
description:
Provide and use some CP0 accessor functions instead of M[TF]C0 macros
for readability.
While here convert some other M[TF]C0 uses to already exising accessor
functions, e.g. mipsNN_cp0_ebase_read
diffstat:
sys/arch/evbmips/ingenic/clock.c | 7 +-
sys/arch/evbmips/ingenic/cpu.c | 17 ++-
sys/arch/evbmips/ingenic/intr.c | 27 +++--
sys/arch/evbmips/ingenic/machdep.c | 13 +-
sys/arch/evbmips/ingenic/mainbus.c | 8 +-
sys/arch/mips/conf/files.ingenic | 3 +-
sys/arch/mips/ingenic/ingenic_coreregs.h | 70 ++++++++++++++
sys/arch/mips/ingenic/ingenic_regs.h | 43 +--------
sys/arch/mips/ingenic/ingenic_var.h | 12 ++-
sys/arch/mips/mips/locore_ingenic.S | 150 +++++++++++++++++++++++++++++++
10 files changed, 274 insertions(+), 76 deletions(-)
diffs (truncated from 593 to 300 lines):
diff -r 3b1c5a228362 -r 4e93e176eff8 sys/arch/evbmips/ingenic/clock.c
--- a/sys/arch/evbmips/ingenic/clock.c Sun May 21 06:19:37 2017 +0000
+++ b/sys/arch/evbmips/ingenic/clock.c Sun May 21 06:49:12 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: clock.c,v 1.9 2017/05/19 07:40:58 skrll Exp $ */
+/* $NetBSD: clock.c,v 1.10 2017/05/21 06:49:12 skrll Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.9 2017/05/19 07:40:58 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.10 2017/05/21 06:49:12 skrll Exp $");
#include "opt_multiprocessor.h"
@@ -38,6 +38,7 @@
#include <sys/systm.h>
#include <sys/timetc.h>
+#include <mips/ingenic/ingenic_var.h>
#include <mips/ingenic/ingenic_regs.h>
#include "opt_ingenic.h"
@@ -236,7 +237,7 @@
* XXX
* needs to take the IPI lock and ping all online CPUs, not just core 1
*/
- MTC0(1 << IPI_CLOCK, 20, 1);
+ mips_cp0_corembox_write(1, 1 << IPI_CLOCK);
#endif
hardclock(cf);
splx(s);
diff -r 3b1c5a228362 -r 4e93e176eff8 sys/arch/evbmips/ingenic/cpu.c
--- a/sys/arch/evbmips/ingenic/cpu.c Sun May 21 06:19:37 2017 +0000
+++ b/sys/arch/evbmips/ingenic/cpu.c Sun May 21 06:49:12 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.3 2017/05/19 07:40:58 skrll Exp $ */
+/* $NetBSD: cpu.c,v 1.4 2017/05/21 06:49:12 skrll Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.3 2017/05/19 07:40:58 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.4 2017/05/21 06:49:12 skrll Exp $");
#include "opt_ingenic.h"
#include "opt_multiprocessor.h"
@@ -47,8 +47,9 @@
#include <sys/cpu.h>
#include <mips/locore.h>
-#include <mips/asm.h>
+#include <mips/ingenic/ingenic_coreregs.h>
#include <mips/ingenic/ingenic_regs.h>
+#include <mips/ingenic/ingenic_var.h>
static int cpu_match(device_t, cfdata_t, void *);
static void cpu_attach(device_t, device_t, void *);
@@ -85,14 +86,16 @@
ci = startup_cpu_info;
wbflush();
vec = (uint32_t)&ingenic_wakeup;
- reg = MFC0(12, 4); /* reset entry reg */
+ reg = mips_cp0_corereim_read();
reg &= ~REIM_ENTRY_M;
reg |= vec;
- MTC0(reg, 12, 4);
- reg = MFC0(12, 2); /* core control reg */
+ mips_cp0_corereim_write(reg);
+
+ reg = mips_cp0_corectrl_read();
reg |= CC_RPC1; /* use our exception vector */
reg &= ~CC_SW_RST1; /* get core 1 out of reset */
- MTC0(reg, 12, 2);
+ mips_cp0_corectrl_write(reg);
+
while ((!kcpuset_isset(cpus_hatched, cpu_index(startup_cpu_info))) && (bail > 0)) {
delay(1000);
bail--;
diff -r 3b1c5a228362 -r 4e93e176eff8 sys/arch/evbmips/ingenic/intr.c
--- a/sys/arch/evbmips/ingenic/intr.c Sun May 21 06:19:37 2017 +0000
+++ b/sys/arch/evbmips/ingenic/intr.c Sun May 21 06:49:12 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.c,v 1.12 2016/08/27 05:52:43 skrll Exp $ */
+/* $NetBSD: intr.c,v 1.13 2017/05/21 06:49:12 skrll Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.12 2016/08/27 05:52:43 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.13 2017/05/21 06:49:12 skrll Exp $");
#define __INTR_PRIVATE
@@ -44,7 +44,9 @@
#include <mips/locore.h>
#include <machine/intr.h>
+#include <mips/ingenic/ingenic_var.h>
#include <mips/ingenic/ingenic_regs.h>
+#include <mips/ingenic/ingenic_coreregs.h>
#include "opt_ingenic.h"
@@ -126,14 +128,15 @@
writereg(JZ_ICMR1, 0xffffffff);
/* allow peripheral interrupts to core 0 only */
- reg = MFC0(12, 4); /* reset entry and interrupts */
+ reg = mips_cp0_corereim_read();
reg &= 0xffff0000;
reg |= REIM_IRQ0_M | REIM_MIRQ0_M;
#ifdef MULTIPROCESSOR
reg |= REIM_MIRQ1_M;
#endif
- MTC0(reg, 12, 4);
- MTC0(0, 20, 1); /* ping the 2nd core */
+ mips_cp0_corereim_write(reg);
+
+ mips_cp0_corembox_write(1, 0); /* ping the 2nd core */
DPRINTF("%s %08x\n", __func__, reg);
}
@@ -146,12 +149,12 @@
#if 0
snprintf(buffer, 256, "pending: %08x CR %08x\n", ipending,
- MFC0(MIPS_COP_0_CAUSE, 0));
+ mipsNN_cp0_cause_read());
ingenic_puts(buffer);
#endif
#endif
/* see which core we're on */
- id = MFC0(15, 1) & 7;
+ id = mipsNN_cp0_ebase_read() & 7;
/*
* XXX
@@ -166,12 +169,12 @@
int s = splsched();
/* read pending IPIs */
- reg = MFC0(12, 3);
+ reg = mips_cp0_corestatus_read();
if (id == 0) {
if (reg & CS_MIRQ0_P) {
#ifdef MULTIPROCESSOR
uint32_t tag;
- tag = MFC0(CP0_CORE_MBOX, 0);
+ tag = mips_cp0_corembox_read(id);
ipi_process(curcpu(), tag);
#ifdef INGENIC_INTR_DEBUG
@@ -182,13 +185,13 @@
#endif
reg &= (~CS_MIRQ0_P);
/* clear it */
- MTC0(reg, 12, 3);
+ mips_cp0_corestatus_write(reg);
}
} else if (id == 1) {
if (reg & CS_MIRQ1_P) {
#ifdef MULTIPROCESSOR
uint32_t tag;
- tag = MFC0(CP0_CORE_MBOX, 1);
+ tag = mips_cp0_corembox_read(id);
ingenic_puts("1");
if (tag & 0x400)
hardclock(cf);
@@ -201,7 +204,7 @@
#endif
reg &= (~CS_MIRQ1_P);
/* clear it */
- MTC0(reg, 12, 3);
+ mips_cp0_corestatus_write(reg);
}
}
splx(s);
diff -r 3b1c5a228362 -r 4e93e176eff8 sys/arch/evbmips/ingenic/machdep.c
--- a/sys/arch/evbmips/ingenic/machdep.c Sun May 21 06:19:37 2017 +0000
+++ b/sys/arch/evbmips/ingenic/machdep.c Sun May 21 06:49:12 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.13 2017/05/19 07:40:58 skrll Exp $ */
+/* $NetBSD: machdep.c,v 1.14 2017/05/21 06:49:12 skrll Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.13 2017/05/19 07:40:58 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.14 2017/05/21 06:49:12 skrll Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@@ -61,6 +61,7 @@
#include <mips/locore.h>
#include <mips/cpuregs.h>
+#include <mips/ingenic/ingenic_coreregs.h>
#include <mips/ingenic/ingenic_regs.h>
#include <mips/ingenic/ingenic_var.h>
@@ -128,12 +129,12 @@
uint32_t reg;
/* enable IPIs for this core */
- reg = MFC0(12, 4); /* reset entry and interrupts */
+ reg = mips_cp0_corereim_read();
if (cpu_index(ci) == 1) {
reg |= REIM_MIRQ1_M;
} else
reg |= REIM_MIRQ0_M;
- MTC0(reg, 12, 4);
+ mips_cp0_corereim_write(reg);
printf("%s %d %08x\n", __func__, cpu_index(ci), reg);
}
@@ -147,9 +148,9 @@
mutex_enter(&ingenic_ipi_lock);
if (kcpuset_isset(cpus_running, cpu_index(ci))) {
if (cpu_index(ci) == 0) {
- MTC0(msg, CP0_CORE_MBOX, 0);
+ mips_cp0_corembox_write(msg, 0);
} else {
- MTC0(msg, CP0_CORE_MBOX, 1);
+ mips_cp0_corembox_write(msg, 1);
}
}
mutex_exit(&ingenic_ipi_lock);
diff -r 3b1c5a228362 -r 4e93e176eff8 sys/arch/evbmips/ingenic/mainbus.c
--- a/sys/arch/evbmips/ingenic/mainbus.c Sun May 21 06:19:37 2017 +0000
+++ b/sys/arch/evbmips/ingenic/mainbus.c Sun May 21 06:49:12 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mainbus.c,v 1.6 2017/05/19 07:40:58 skrll Exp $ */
+/* $NetBSD: mainbus.c,v 1.7 2017/05/21 06:49:12 skrll Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.6 2017/05/19 07:40:58 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.7 2017/05/21 06:49:12 skrll Exp $");
#include "opt_multiprocessor.h"
@@ -95,11 +95,11 @@
printf("TMR: %08x\n", readreg(JZ_TC_TMR));
/* send ourselves an IPI */
- MTC0(0x12345678, CP0_CORE_MBOX, 0);
+ mips_cp0_corembox_write(0x12345678, 0);
delay(1000);
/* send the other core an IPI */
- MTC0(0x12345678, CP0_CORE_MBOX, 1);
+ mips_cp0_corembox_write(0x12345678, 1);
delay(1000);
#endif
}
diff -r 3b1c5a228362 -r 4e93e176eff8 sys/arch/mips/conf/files.ingenic
--- a/sys/arch/mips/conf/files.ingenic Sun May 21 06:19:37 2017 +0000
+++ b/sys/arch/mips/conf/files.ingenic Sun May 21 06:49:12 2017 +0000
@@ -1,6 +1,7 @@
-# $NetBSD: files.ingenic,v 1.9 2017/05/19 07:30:24 skrll Exp $
+# $NetBSD: files.ingenic,v 1.10 2017/05/21 06:49:13 skrll Exp $
file arch/mips/mips/bus_dma.c
+file arch/mips/mips/locore_ingenic.S
include "dev/scsipi/files.scsipi" # SCSI devices
include "dev/ata/files.ata" # ATA devices
diff -r 3b1c5a228362 -r 4e93e176eff8 sys/arch/mips/ingenic/ingenic_coreregs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/ingenic/ingenic_coreregs.h Sun May 21 06:49:12 2017 +0000
@@ -0,0 +1,70 @@
+/* $NetBSD: ingenic_coreregs.h,v 1.1 2017/05/21 06:49:13 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2014 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
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