[src/trunk]: src/sys/arch use CR8 instead of LAPIC Task Priority register on ...

[nonaka <nonaka%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/2c49f68b72b5
branches:  trunk
changeset: 823410:2c49f68b72b5
user:      nonaka <nonaka%NetBSD.org@localhost>
date:      Sat Apr 22 04:29:31 2017 +0000

description:
use CR8 instead of LAPIC Task Priority register on x86-64.

diffstat:

 sys/arch/i386/i386/autoconf.c    |   6 +++---
 sys/arch/x86/include/i82489var.h |   4 +++-
 sys/arch/x86/x86/cpu.c           |  10 +++-------
 sys/arch/x86/x86/lapic.c         |  18 +++++++++++++++---
 4 files changed, 24 insertions(+), 14 deletions(-)

diffs (119 lines):

diff -r 40ccec6ca456 -r 2c49f68b72b5 sys/arch/i386/i386/autoconf.c
--- a/sys/arch/i386/i386/autoconf.c     Sat Apr 22 04:25:09 2017 +0000
+++ b/sys/arch/i386/i386/autoconf.c     Sat Apr 22 04:29:31 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: autoconf.c,v 1.101 2016/10/16 10:24:59 maxv Exp $      */
+/*     $NetBSD: autoconf.c,v 1.102 2017/04/22 04:29:31 nonaka Exp $    */
 
 /*-
  * Copyright (c) 1990 The Regents of the University of California.
@@ -46,7 +46,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.101 2016/10/16 10:24:59 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.102 2017/04/22 04:29:31 nonaka Exp $");
 
 #include "opt_compat_oldboot.h"
 #include "opt_intrdebug.h"
@@ -131,6 +131,6 @@
 
        spl0();
 #if NLAPIC > 0
-       i82489_writereg(LAPIC_TPRI, 0);
+       lapic_write_tpri(0);
 #endif
 }
diff -r 40ccec6ca456 -r 2c49f68b72b5 sys/arch/x86/include/i82489var.h
--- a/sys/arch/x86/include/i82489var.h  Sat Apr 22 04:25:09 2017 +0000
+++ b/sys/arch/x86/include/i82489var.h  Sat Apr 22 04:29:31 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: i82489var.h,v 1.17 2017/04/19 06:43:05 nonaka Exp $    */
+/*     $NetBSD: i82489var.h,v 1.18 2017/04/22 04:29:31 nonaka Exp $    */
 
 /*-
  * Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -104,4 +104,6 @@
 extern void lapic_calibrate_timer(struct cpu_info *ci);
 extern void lapic_initclocks(void);
 
+extern void lapic_write_tpri(uint32_t);
+
 #endif
diff -r 40ccec6ca456 -r 2c49f68b72b5 sys/arch/x86/x86/cpu.c
--- a/sys/arch/x86/x86/cpu.c    Sat Apr 22 04:25:09 2017 +0000
+++ b/sys/arch/x86/x86/cpu.c    Sat Apr 22 04:29:31 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpu.c,v 1.123 2017/02/11 14:11:24 maxv Exp $   */
+/*     $NetBSD: cpu.c,v 1.124 2017/04/22 04:29:31 nonaka Exp $ */
 
 /*-
  * Copyright (c) 2000-2012 NetBSD Foundation, Inc.
@@ -62,7 +62,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.123 2017/02/11 14:11:24 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.124 2017/04/22 04:29:31 nonaka Exp $");
 
 #include "opt_ddb.h"
 #include "opt_mpbios.h"                /* for MPDEBUG */
@@ -879,11 +879,7 @@
        cpu_get_tsc_freq(ci);
 
        s = splhigh();
-#ifdef i386
-       i82489_writereg(LAPIC_TPRI, 0);
-#else
-       lcr8(0);
-#endif
+       lapic_write_tpri(0);
        x86_enable_intr();
        splx(s);
        x86_errata();
diff -r 40ccec6ca456 -r 2c49f68b72b5 sys/arch/x86/x86/lapic.c
--- a/sys/arch/x86/x86/lapic.c  Sat Apr 22 04:25:09 2017 +0000
+++ b/sys/arch/x86/x86/lapic.c  Sat Apr 22 04:29:31 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: lapic.c,v 1.55 2017/04/22 04:24:26 nonaka Exp $        */
+/*     $NetBSD: lapic.c,v 1.56 2017/04/22 04:29:31 nonaka Exp $        */
 
 /*-
  * Copyright (c) 2000, 2008 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.55 2017/04/22 04:24:26 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: lapic.c,v 1.56 2017/04/22 04:29:31 nonaka Exp $");
 
 #include "opt_ddb.h"
 #include "opt_mpbios.h"                /* for MPDEBUG */
@@ -89,6 +89,18 @@
        .pic_delroute = lapic_setup,
 };
 
+void
+lapic_write_tpri(uint32_t val)
+{
+
+       val &= LAPIC_TPRI_MASK;
+#ifdef i386
+       i82489_writereg(LAPIC_TPRI, val);
+#else
+       lcr8(val >> 4);
+#endif
+}
+
 static void
 lapic_map(paddr_t lapic_base)
 {
@@ -130,7 +142,7 @@
        cpu_init_first();       /* catch up to changed cpu_number() */
 #endif
 
-       i82489_writereg(LAPIC_TPRI, 0);
+       lapic_write_tpri(0);
        x86_enable_intr();
 }