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[src/trunk]: src/sys/arch/arm Add support for the ARM1176JZS
details: https://anonhg.NetBSD.org/src/rev/f9f1962dd90a
branches: trunk
changeset: 780362:f9f1962dd90a
user: skrll <skrll%NetBSD.org@localhost>
date: Sat Jul 21 12:19:15 2012 +0000
description:
Add support for the ARM1176JZS
diffstat:
sys/arch/arm/arm/cpufunc.c | 117 ++++++++++++++---
sys/arch/arm/arm/cpufunc_asm_arm1136.S | 128 +------------------
sys/arch/arm/arm/cpufunc_asm_arm11x6.S | 219 +++++++++++++++++++++++++++++++++
sys/arch/arm/conf/files.arm | 3 +-
sys/arch/arm/include/cpufunc.h | 19 +-
5 files changed, 329 insertions(+), 157 deletions(-)
diffs (truncated from 634 to 300 lines):
diff -r 6ae0da8e9d50 -r f9f1962dd90a sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c Sat Jul 21 11:45:04 2012 +0000
+++ b/sys/arch/arm/arm/cpufunc.c Sat Jul 21 12:19:15 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.107 2012/07/14 12:59:55 hans Exp $ */
+/* $NetBSD: cpufunc.c,v 1.108 2012/07/21 12:19:15 skrll Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.107 2012/07/14 12:59:55 hans Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.108 2012/07/21 12:19:15 skrll Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -747,7 +747,7 @@
.cf_control = cpufunc_control,
.cf_domains = cpufunc_domains,
- .cf_setttb = arm1136_setttb,
+ .cf_setttb = arm11x6_setttb,
.cf_faultstatus = cpufunc_faultstatus,
.cf_faultaddress = cpufunc_faultaddress,
@@ -762,25 +762,25 @@
/* Cache operations */
- .cf_icache_sync_all = arm1136_icache_sync_all, /* 411920 */
- .cf_icache_sync_range = arm1136_icache_sync_range, /* 371025 */
-
- .cf_dcache_wbinv_all = arm1136_dcache_wbinv_all, /* 411920 */
+ .cf_icache_sync_all = arm11x6_icache_sync_all, /* 411920 */
+ .cf_icache_sync_range = arm11x6_icache_sync_range, /* 371025 */
+
+ .cf_dcache_wbinv_all = arm11x6_dcache_wbinv_all, /* 411920 */
.cf_dcache_wbinv_range = armv6_dcache_wbinv_range,
.cf_dcache_inv_range = armv6_dcache_inv_range,
.cf_dcache_wb_range = armv6_dcache_wb_range,
- .cf_idcache_wbinv_all = arm1136_idcache_wbinv_all, /* 411920 */
- .cf_idcache_wbinv_range = arm1136_idcache_wbinv_range, /* 371025 */
+ .cf_idcache_wbinv_all = arm11x6_idcache_wbinv_all, /* 411920 */
+ .cf_idcache_wbinv_range = arm11x6_idcache_wbinv_range, /* 371025 */
/* Other functions */
- .cf_flush_prefetchbuf = arm1136_flush_prefetchbuf,
+ .cf_flush_prefetchbuf = arm11x6_flush_prefetchbuf,
.cf_drain_writebuf = arm11_drain_writebuf,
.cf_flush_brnchtgt_C = cpufunc_nullop,
.cf_flush_brnchtgt_E = (void *)cpufunc_nullop,
- .cf_sleep = arm11_sleep,
+ .cf_sleep = arm11_sleep, /* arm1136_sleep_rev0 */
/* Soft functions */
@@ -789,11 +789,70 @@
.cf_context_switch = arm11_context_switch,
- .cf_setup = arm1136_setup
+ .cf_setup = arm11x6_setup
};
#endif /* CPU_ARM1136 */
+#ifdef CPU_ARM1176
+struct cpu_functions arm1176_cpufuncs = {
+ /* CPU functions */
+
+ .cf_id = cpufunc_id,
+ .cf_cpwait = cpufunc_nullop,
+
+ /* MMU functions */
+
+ .cf_control = cpufunc_control,
+ .cf_domains = cpufunc_domains,
+ .cf_setttb = arm11x6_setttb,
+ .cf_faultstatus = cpufunc_faultstatus,
+ .cf_faultaddress = cpufunc_faultaddress,
+
+ /* TLB functions */
+
+ .cf_tlb_flushID = arm11_tlb_flushID,
+ .cf_tlb_flushID_SE = arm11_tlb_flushID_SE,
+ .cf_tlb_flushI = arm11_tlb_flushI,
+ .cf_tlb_flushI_SE = arm11_tlb_flushI_SE,
+ .cf_tlb_flushD = arm11_tlb_flushD,
+ .cf_tlb_flushD_SE = arm11_tlb_flushD_SE,
+
+ /* Cache operations */
+
+ .cf_icache_sync_all = arm11x6_icache_sync_all, /* 415045 */
+ .cf_icache_sync_range = arm11x6_icache_sync_range, /* 371367 */
+
+ .cf_dcache_wbinv_all = arm11x6_dcache_wbinv_all, /* 415045 */
+ .cf_dcache_wbinv_range = armv6_dcache_wbinv_range,
+ .cf_dcache_inv_range = armv6_dcache_inv_range,
+ .cf_dcache_wb_range = armv6_dcache_wb_range,
+
+ .cf_idcache_wbinv_all = arm11x6_idcache_wbinv_all, /* 415045 */
+ .cf_idcache_wbinv_range = arm11x6_idcache_wbinv_range, /* 371367 */
+
+ /* Other functions */
+
+ .cf_flush_prefetchbuf = arm11x6_flush_prefetchbuf,
+ .cf_drain_writebuf = arm11_drain_writebuf,
+ .cf_flush_brnchtgt_C = cpufunc_nullop,
+ .cf_flush_brnchtgt_E = (void *)cpufunc_nullop,
+
+ .cf_sleep = arm11x6_sleep, /* no ref. */
+
+ /* Soft functions */
+
+ .cf_dataabt_fixup = cpufunc_null_fixup,
+ .cf_prefetchabt_fixup = cpufunc_null_fixup,
+
+ .cf_context_switch = arm11_context_switch,
+
+ .cf_setup = arm11x6_setup
+
+};
+#endif /* CPU_ARM1176 */
+
+
#ifdef CPU_ARM11MPCORE
struct cpu_functions arm11mpcore_cpufuncs = {
/* CPU functions */
@@ -1650,12 +1709,18 @@
cputype == CPU_ID_ARM1176JZS) {
cpufuncs = arm11_cpufuncs;
#if defined(CPU_ARM1136)
- if (cputype != CPU_ID_ARM1176JZS) {
+ if (cputype == CPU_ID_ARM1136JS &&
+ cputype == CPU_ID_ARM1136JSR1) {
cpufuncs = arm1136_cpufuncs;
if (cputype == CPU_ID_ARM1136JS)
cpufuncs.cf_sleep = arm1136_sleep_rev0;
}
#endif
+#if defined(CPU_ARM1176)
+ if (cputype == CPU_ID_ARM1176JZS) {
+ cpufuncs = arm1176_cpufuncs;
+ }
+#endif
cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
cpu_do_powersave = 1; /* Enable powersave */
get_cachetype_cp15();
@@ -2249,7 +2314,7 @@
defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
- defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_ARM1136) || \
+ defined(CPU_ARM10) || defined(CPU_ARM11) || \
defined(CPU_FA526) || defined(CPU_CORTEX) || defined(CPU_SHEEVA)
#define IGN 0
@@ -2860,10 +2925,9 @@
#endif /* CPU_CORTEX */
-
-#if defined(CPU_ARM1136)
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
void
-arm1136_setup(char *args)
+arm11x6_setup(char *args)
{
int cpuctrl, cpuctrl_wax;
uint32_t auxctrl, auxctrl_wax;
@@ -2918,7 +2982,8 @@
auxctrl = 0;
auxctrl_wax = ~0;
- /* This options enables the workaround for the 364296 ARM1136
+ /*
+ * This options enables the workaround for the 364296 ARM1136
* r0pX errata (possible cache data corruption with
* hit-under-miss enabled). It sets the undocumented bit 31 in
* the auxiliary control register and the FI bit in the control
@@ -2932,6 +2997,14 @@
auxctrl_wax = ~ARM11R0_AUXCTL_PFI;
}
+ /*
+ * Enable an errata workaround
+ */
+ if ((cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM1176JZS) { /* ARM1176JZSr0 */
+ auxctrl = ARM1176_AUXCTL_PHD;
+ auxctrl_wax = ~ARM1176_AUXCTL_PHD;
+ }
+
/* Clear out the cache */
cpu_idcache_wbinv_all();
@@ -2946,17 +3019,17 @@
cpu_control(~cpuctrl_wax, cpuctrl);
__asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t"
- "bic %1, %0, %2\n\t"
- "eor %1, %0, %3\n\t"
+ "and %1, %0, %2\n\t"
+ "orr %1, %1, %3\n\t"
"teq %0, %1\n\t"
"mcrne p15, 0, %1, c1, c0, 1\n\t"
: "=r"(tmp), "=r"(tmp2) :
- "r"(~auxctrl_wax), "r"(auxctrl));
+ "r"(auxctrl_wax), "r"(auxctrl));
/* And again. */
cpu_idcache_wbinv_all();
}
-#endif /* CPU_ARM1136 */
+#endif /* CPU_ARM1136 || CPU_ARM1176 */
#ifdef CPU_SA110
struct cpu_option sa110_options[] = {
diff -r 6ae0da8e9d50 -r f9f1962dd90a sys/arch/arm/arm/cpufunc_asm_arm1136.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm1136.S Sat Jul 21 11:45:04 2012 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm1136.S Sat Jul 21 12:19:15 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm1136.S,v 1.2 2008/04/27 18:58:43 matt Exp $ */
+/* $NetBSD: cpufunc_asm_arm1136.S,v 1.3 2012/07/21 12:19:15 skrll Exp $ */
/*
* Copyright (c) 2007 Microsoft
@@ -33,131 +33,7 @@
#include <machine/cpu.h>
#include <machine/asm.h>
-RCSID("$NetBSD: cpufunc_asm_arm1136.S,v 1.2 2008/04/27 18:58:43 matt Exp $")
-
-#if 0
-#define Invalidate_I_cache(Rtmp1, Rtmp2) \
- mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */
-#else
-/*
- * Workaround Erratum 411920
- *
- * - value of arg 'reg' Should Be Zero
- */
-#define Invalidate_I_cache(Rtmp1, Rtmp2) \
- mov Rtmp1, #0; /* SBZ */ \
- mrs Rtmp2, cpsr; \
- cpsid ifa; \
- mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
- mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
- mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
- mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
- msr cpsr_cx, Rtmp2; \
- nop; \
- nop; \
- nop; \
- nop; \
- nop; \
- nop; \
- nop; \
- nop; \
- nop; \
- nop; \
- nop;
-#endif
-
-#if 1
-#define Flush_D_cache(reg) \
- mov reg, #0; /* SBZ */ \
- mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
- mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
-#else
-#define Flush_D_cache(reg) \
-1: mov reg, #0; /* SBZ */ \
- mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
- mrc p15, 0, reg, C7, C10, 6;/* Read Cache Dirty Status Register */ \
- ands reg, reg, #01; /* Check if it is clean */ \
- bne 1b; /* loop if not */ \
- mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
-#endif
-
-ENTRY(arm1136_setttb)
-#ifdef PMAP_CACHE_VIVT
- Flush_D_cache(r1)
- Invalidate_I_cache(r1, r2)
-#endif
- mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
- mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLBs */
- mcr p15, 0, r1, c7, c10, 4 /* drain write buffer */
- RET
-
-ENTRY_NP(arm1136_idcache_wbinv_all)
- Flush_D_cache(r0)
- Invalidate_I_cache(r0, r1)
- RET
-
-ENTRY_NP(arm1136_dcache_wbinv_all)
- Flush_D_cache(r0)
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