[src/netbsd-6]: src/sys/arch/arm/marvell sys/arch/arm/marvell/mvsoc.c patch

[riz <riz%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/9942aaa97cd9
branches:  netbsd-6
changeset: 775565:9942aaa97cd9
user:      riz <riz%NetBSD.org@localhost>
date:      Tue Dec 11 04:44:02 2012 +0000

description:
sys/arch/arm/marvell/mvsoc.c                    patch
sys/arch/arm/marvell/mvsocreg.h                 patch

        Add CLKGATING_BIT, enable it for some 88F6281 devices, and don't
        configure devices if their clock is disabled.
        [msaitoh, ticket #737]

diffstat:

 sys/arch/arm/marvell/mvsoc.c    |  42 ++++++++++++++++++++++++++++++++--------
 sys/arch/arm/marvell/mvsocreg.h |   5 +++-
 2 files changed, 37 insertions(+), 10 deletions(-)

diffs (105 lines):

diff -r 5b2895a92bfe -r 9942aaa97cd9 sys/arch/arm/marvell/mvsoc.c
--- a/sys/arch/arm/marvell/mvsoc.c      Tue Dec 11 04:31:52 2012 +0000
+++ b/sys/arch/arm/marvell/mvsoc.c      Tue Dec 11 04:44:02 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mvsoc.c,v 1.5 2012/02/12 16:34:07 matt Exp $   */
+/*     $NetBSD: mvsoc.c,v 1.5.2.1 2012/12/11 04:44:02 riz Exp $        */
 /*
  * Copyright (c) 2007, 2008 KIYOHARA Takashi
  * All rights reserved.
@@ -26,7 +26,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.5 2012/02/12 16:34:07 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.5.2.1 2012/12/11 04:44:02 riz Exp $");
 
 #include "opt_cputypes.h"
 #include "opt_mvsoc.h"
@@ -193,6 +193,7 @@
        int unit;
        bus_size_t offset;
        int irq;
+       uint32_t clkpwr_bit;
 } mvsoc_periphs[] = {
 #if defined(ORION)
     { ORION_1(88F1181),        "mvsoctmr",0, MVSOC_TMR_BASE,   IRQ_DEFAULT },
@@ -333,15 +334,23 @@
     { KIRKWOOD(88F6281),"mvsocrtc",0, KIRKWOOD_RTC_BASE,IRQ_DEFAULT },
     { KIRKWOOD(88F6281),"com",     0, MVSOC_COM0_BASE, KIRKWOOD_IRQ_UART0INT },
     { KIRKWOOD(88F6281),"com",     1, MVSOC_COM1_BASE, KIRKWOOD_IRQ_UART1INT },
-    { KIRKWOOD(88F6281),"ehci",    0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT },
+    { KIRKWOOD(88F6281),"ehci",    0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT,
+                                       MVSOC_MLMB_CLKGATING_BIT(3) },
 //  { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,? },
     { KIRKWOOD(88F6281),"gttwsi",  0, MVSOC_TWSI_BASE, KIRKWOOD_IRQ_TWSI },
-    { KIRKWOOD(88F6281),"mvcesa",  0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT},
-    { KIRKWOOD(88F6281),"mvgbec",  0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT },
-    { KIRKWOOD(88F6281),"mvgbec",  1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT },
-    { KIRKWOOD(88F6281),"mvpex",   0, MVSOC_PEX_BASE,  KIRKWOOD_IRQ_PEX0INT },
-    { KIRKWOOD(88F6281),"mvsata",  0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA },
-    { KIRKWOOD(88F6281),"mvsdio",  0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT },
+    { KIRKWOOD(88F6281),"mvcesa",  0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT,
+                                       MVSOC_MLMB_CLKGATING_BIT(17) },
+    { KIRKWOOD(88F6281),"mvgbec",  0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT,
+                                       MVSOC_MLMB_CLKGATING_BIT(0) },
+    { KIRKWOOD(88F6281),"mvgbec",  1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT,
+                                       MVSOC_MLMB_CLKGATING_BIT(19) },
+    { KIRKWOOD(88F6281),"mvpex",   0, MVSOC_PEX_BASE,  KIRKWOOD_IRQ_PEX0INT,
+                                       MVSOC_MLMB_CLKGATING_BIT(2) },
+    { KIRKWOOD(88F6281),"mvsata",  0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA,
+                                       MVSOC_MLMB_CLKGATING_BIT(14) |
+                                       MVSOC_MLMB_CLKGATING_BIT(15) },
+    { KIRKWOOD(88F6281),"mvsdio",  0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT,
+                                       MVSOC_MLMB_CLKGATING_BIT(4) },
 #endif
 
 #if defined(MV78XX0)
@@ -381,6 +390,7 @@
        struct marvell_attach_args mva;
        uint16_t model;
        uint8_t rev;
+       uint32_t clkpwr, clkpwrbit;
        int i;
 
        sc->sc_dev = self;
@@ -420,6 +430,20 @@
                if (mvsoc_periphs[i].model != model)
                        continue;
 
+               /* Skip clock disabled devices */
+               clkpwrbit = mvsoc_periphs[i].clkpwr_bit;
+               if (clkpwrbit != 0) {
+                       clkpwr = read_mlmbreg(MVSOC_MLMB_CLKGATING);
+
+                       if ((clkpwr & clkpwrbit) == 0) {
+                               aprint_normal("%s: %s%d clock disabled\n",
+                                   device_xname(self),
+                                   mvsoc_periphs[i].name,
+                                   mvsoc_periphs[i].unit);
+                               continue;
+                       }
+               }
+
                mva.mva_name = mvsoc_periphs[i].name;
                mva.mva_model = model;
                mva.mva_revision = rev;
diff -r 5b2895a92bfe -r 9942aaa97cd9 sys/arch/arm/marvell/mvsocreg.h
--- a/sys/arch/arm/marvell/mvsocreg.h   Tue Dec 11 04:31:52 2012 +0000
+++ b/sys/arch/arm/marvell/mvsocreg.h   Tue Dec 11 04:44:02 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mvsocreg.h,v 1.2 2011/02/01 22:54:24 jakllsch Exp $    */
+/*     $NetBSD: mvsocreg.h,v 1.2.12.1 2012/12/11 04:44:03 riz Exp $    */
 /*
  * Copyright (c) 2007, 2008 KIYOHARA Takashi
  * All rights reserved.
@@ -110,6 +110,9 @@
 #define MVSOC_MLMB_MLMBICR               0x110 /*Mb-L to Mb Bridge Intr Cause*/
 #define MVSOC_MLMB_MLMBIMR               0x114 /*Mb-L to Mb Bridge Intr Mask */
 
+#define MVSOC_MLMB_CLKGATING             0x11c /* Clock Gating Control */
+#define MVSOC_MLMB_CLKGATING_BIT(n)      (1 << (n))
+
 #define MVSOC_MLMB_L2CFG                 0x128 /* L2 Cache Config */
 
 #define MVSOC_TMR_BASE                 (MVSOC_MLMB_BASE + 0x0300)