[src/trunk]: src/sys/dev/pci Fix the checking of jumbo frame function though ...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/e39bc0977553
branches:  trunk
changeset: 750535:e39bc0977553
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Tue Jan 05 10:02:01 2010 +0000

description:
Fix the checking of jumbo frame function though I don't know whether
the function wokrs or not...

 Remove the extra macro definition for the offset 0x1a in EEPROM.

diffstat:

 sys/dev/pci/if_wm.c    |  48 ++++++++++++++++++++++++++++++++++++------------
 sys/dev/pci/if_wmreg.h |   9 +++++----
 2 files changed, 41 insertions(+), 16 deletions(-)

diffs (130 lines):

diff -r 49ac72da0d18 -r e39bc0977553 sys/dev/pci/if_wm.c
--- a/sys/dev/pci/if_wm.c       Tue Jan 05 09:31:21 2010 +0000
+++ b/sys/dev/pci/if_wm.c       Tue Jan 05 10:02:01 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_wm.c,v 1.186 2010/01/05 09:31:21 msaitoh Exp $      */
+/*     $NetBSD: if_wm.c,v 1.187 2010/01/05 10:02:01 msaitoh Exp $      */
 
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -76,7 +76,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.186 2010/01/05 09:31:21 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.187 2010/01/05 10:02:01 msaitoh Exp $");
 
 #include "bpfilter.h"
 #include "rnd.h"
@@ -941,7 +941,7 @@
        prop_data_t ea;
        prop_number_t pn;
        uint8_t enaddr[ETHER_ADDR_LEN];
-       uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin;
+       uint16_t myea[ETHER_ADDR_LEN / 2], cfg1, cfg2, swdpin, io3;
        pcireg_t preg, memtype;
        uint32_t reg;
 
@@ -1576,9 +1576,34 @@
        IFQ_SET_MAXLEN(&ifp->if_snd, max(WM_IFQUEUELEN, IFQ_MAXLEN));
        IFQ_SET_READY(&ifp->if_snd);
 
-       if (sc->sc_type != WM_T_82573 && sc->sc_type != WM_T_82574 &&
-           sc->sc_type != WM_T_82583 && sc->sc_type != WM_T_ICH8)
+       /* Check for jumbo frame */
+       switch (sc->sc_type) {
+       case WM_T_82573:
+               /* XXX limited to 9234 if ASPM is disabled */
+               wm_read_eeprom(sc, EEPROM_INIT_3GIO_3, 1, &io3);
+               if ((io3 & EEPROM_3GIO_3_ASPM_MASK) != 0)
+                       sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
+               break;
+       case WM_T_82571:
+       case WM_T_82572:
+       case WM_T_82574:
+       case WM_T_80003:
+       case WM_T_ICH9:
+       case WM_T_ICH10:
+               /* XXX limited to 9234 */
                sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
+               break;
+       case WM_T_82542_2_0:
+       case WM_T_82542_2_1:
+       case WM_T_82583:
+       case WM_T_ICH8:
+               /* No support for jumbo frame */
+               break;
+       default:
+               /* ETHER_MAX_LEN_JUMBO */
+               sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
+               break;
+       }
 
        /*
         * If we're a i82543 or greater, we can support VLANs.
@@ -3483,10 +3508,9 @@
        sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF
            | RCTL_MO(sc->sc_mchash_type);
 
-       /* 82573 doesn't support jumbo frame */
-       if (sc->sc_type != WM_T_82573 && sc->sc_type != WM_T_82574 &&
-           sc->sc_type != WM_T_82583 && sc->sc_type != WM_T_ICH8)
-               sc->sc_rctl |= RCTL_LPE;
+       if (((sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) != 0)
+           && (ifp->if_mtu > ETHERMTU))
+                       sc->sc_rctl |= RCTL_LPE;
 
        if (MCLBYTES == 2048) {
                sc->sc_rctl |= RCTL_2k;
@@ -5689,9 +5713,9 @@
 {
        uint16_t data;
 
-       wm_read_eeprom(sc, NVM_INIT_CONTROL2_REG, 1, &data);
-
-       if ((data & NVM_INIT_CTRL2_MNGM) != 0)
+       wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &data);
+
+       if ((data & EEPROM_CFG2_MNGM_MASK) != 0)
                return 1;
 
        return 0;
diff -r 49ac72da0d18 -r e39bc0977553 sys/dev/pci/if_wmreg.h
--- a/sys/dev/pci/if_wmreg.h    Tue Jan 05 09:31:21 2010 +0000
+++ b/sys/dev/pci/if_wmreg.h    Tue Jan 05 10:02:01 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_wmreg.h,v 1.29 2009/12/29 16:01:21 msaitoh Exp $    */
+/*     $NetBSD: if_wmreg.h,v 1.30 2010/01/05 10:02:01 msaitoh Exp $    */
 
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
@@ -273,6 +273,7 @@
 #define        EEPROM_OFF_MACADDR      0x00    /* MAC address offset */
 #define        EEPROM_OFF_CFG1         0x0a    /* config word 1 */
 #define        EEPROM_OFF_CFG2         0x0f    /* config word 2 */
+#define        EEPROM_INIT_3GIO_3      0x1a    /* PCIe Initial Configuration Word 3 */ 
 #define        EEPROM_OFF_SWDPIN       0x20    /* SWD Pins (Cordova) */
 
 #define        EEPROM_CFG1_LVDID       (1U << 0)
@@ -304,11 +305,14 @@
 #define        EEPROM_CFG2_APM_PME     (1U << 15)
 #define        EEPROM_CFG2_SWDPIO_SHIFT 4
 #define        EEPROM_CFG2_SWDPIO_MASK (0xf << EEPROM_CFG2_SWDPIO_SHIFT)
+#define        EEPROM_CFG2_MNGM_MASK   (3U << 13) /* Manageability Operation mode */
 
 #define        EEPROM_SWDPIN_MASK      0xdf
 #define        EEPROM_SWDPIN_SWDPIN_SHIFT 0
 #define        EEPROM_SWDPIN_SWDPIO_SHIFT 8
 
+#define EEPROM_3GIO_3_ASPM_MASK        (0x3 << 2)      /* Active State PM Support */
+
 #define        WMREG_EERD      0x0014  /* EEPROM read */
 #define        EERD_DONE       0x02    /* done bit */
 #define        EERD_START      0x01    /* First bit for telling part to start operation */
@@ -750,6 +754,3 @@
 
 #define ICH_NVM_SIG_WORD       0x13
 #define ICH_NVM_SIG_MASK       0xc000
-
-#define        NVM_INIT_CONTROL2_REG   0x000f
-#define        NVM_INIT_CTRL2_MNGM     0x6000