[src/trunk]: src/sys/dev/pci Print out negotiated link width and speed for PC...

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/e23e4cd89c3e
branches:  trunk
changeset: 782188:e23e4cd89c3e
user:      matt <matt%NetBSD.org@localhost>
date:      Sat Oct 20 05:57:34 2012 +0000

description:
Print out negotiated link width and speed for PCIe (merged from
matt-nb5-mips64).

diffstat:

 sys/dev/pci/ppb.c |  52 +++++++++++++++++++++++++++++++++++++++++++++++++---
 1 files changed, 49 insertions(+), 3 deletions(-)

diffs (87 lines):

diff -r 9e34b9dbff59 -r e23e4cd89c3e sys/dev/pci/ppb.c
--- a/sys/dev/pci/ppb.c Sat Oct 20 05:33:00 2012 +0000
+++ b/sys/dev/pci/ppb.c Sat Oct 20 05:57:34 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ppb.c,v 1.49 2012/01/29 11:31:38 drochner Exp $        */
+/*     $NetBSD: ppb.c,v 1.50 2012/10/20 05:57:34 matt Exp $    */
 
 /*
  * Copyright (c) 1996, 1998 Christopher G. Demetriou.  All rights reserved.
@@ -31,7 +31,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.49 2012/01/29 11:31:38 drochner Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.50 2012/10/20 05:57:34 matt Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -55,6 +55,10 @@
        pcireg_t sc_pciconfext[48];
 };
 
+static const char pcie_linkspeed_strings[4][5] = {
+       "1.25", "2.5", "5.0", "8.0",
+};
+
 static bool            ppb_resume(device_t, const pmf_qual_t *);
 static bool            ppb_suspend(device_t, const pmf_qual_t *);
 
@@ -83,6 +87,13 @@
        }
 #endif
 
+#ifdef _MIPS_PADDR_T_64BIT
+       /* The LDT HB acts just like a PPB.  */
+       if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIBYTE
+           && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIBYTE_BCM1250_LDTHB)
+               return 1;
+#endif
+
        return 0;
 }
 
@@ -139,7 +150,42 @@
                    __SHIFTOUT(reg, PCI_PCIE_XCAP_TYPE_MASK));
                break;
        }
-       aprint_normal(">\n");
+
+       switch (reg & PCI_PCIE_XCAP_TYPE_MASK) {
+       case PCI_PCIE_XCAP_TYPE_ROOT:
+       case PCI_PCIE_XCAP_TYPE_DOWN:
+       case PCI_PCIE_XCAP_TYPE_PCI2PCIE:
+               reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + 0x0c);
+               u_int mlw = (reg >> 4) & 0x1f;
+               u_int mls = (reg >> 0) & 0x0f;
+               if (mls < __arraycount(pcie_linkspeed_strings)) {
+                       aprint_normal("> x%d @ %sGb/s\n",
+                           mlw, pcie_linkspeed_strings[mls]);
+               } else {
+                       aprint_normal("> x%d @ %d.%dGb/s\n",
+                           mlw, (mls * 25) / 10, (mls * 25) % 10);
+               }
+
+               reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + 0x10);
+               if (reg & __BIT(29)) {  /* DLLA */
+                       u_int lw = (reg >> 20) & 0x1f;
+                       u_int ls = (reg >> 16) & 0x0f;
+                       if (lw != mlw || ls != mls) {
+                               if (ls < __arraycount(pcie_linkspeed_strings)) {
+                                       aprint_normal("> x%d @ %sGb/s\n",
+                                           lw, pcie_linkspeed_strings[ls]);
+                               } else {
+                                       aprint_normal_dev(self,
+                                           "link is x%d @ %d.%dGb/s\n",
+                                           lw, (ls * 25) / 10, (ls * 25) % 10);
+                               }
+                       }
+               }
+               break;
+       default:
+               aprint_normal(">\n");
+               break;
+       }
 
        reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCI_PCIE_SLCSR);
        if (reg & PCI_PCIE_SLCSR_NOTIFY_MASK) {