[src/trunk]: src/sys/arch/bebox/bebox Enable cpu0 I/D cache. Disable cpu1 it.

[kiyohara <kiyohara%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/76d1a6946710
branches:  trunk
changeset: 782199:76d1a6946710
user:      kiyohara <kiyohara%NetBSD.org@localhost>
date:      Sat Oct 20 12:45:22 2012 +0000

description:
Enable cpu0 I/D cache. Disable cpu1 it.

diffstat:

 sys/arch/bebox/bebox/locore.S |  23 ++++++++++++++++++++++-
 1 files changed, 22 insertions(+), 1 deletions(-)

diffs (51 lines):

diff -r 58dfc77ca9ff -r 76d1a6946710 sys/arch/bebox/bebox/locore.S
--- a/sys/arch/bebox/bebox/locore.S     Sat Oct 20 12:37:49 2012 +0000
+++ b/sys/arch/bebox/bebox/locore.S     Sat Oct 20 12:45:22 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.26 2012/10/20 12:13:46 kiyohara Exp $     */
+/*     $NetBSD: locore.S,v 1.27 2012/10/20 12:45:22 kiyohara Exp $     */
 /*     $OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $       */
 
 /*
@@ -49,6 +49,7 @@
 #include <machine/asm.h>
 
 #include <powerpc/spr.h>
+#include <powerpc/oea/hid.h>
 #include <powerpc/oea/spr.h>
 
 /*
@@ -123,6 +124,12 @@
        nop
 
 __start_cpu1:
+       /* Disable data and instruction caches for spinup. */
+       li      8,0
+       mtspr   SPR_HID0,8
+       sync
+       isync
+
 #ifdef MULTIPROCESSOR
        li      3, 0x1          /* CPU ID 1 */
        ba      cpu_spinstart   /* cpu_spinstart(CPU ID) */
@@ -133,6 +140,20 @@
        nop
 
 __start_cpu0:
+       /* Enable data and instruction caches */
+       mfspr   8,SPR_HID0
+       andi.   8,8,(HID0_ICE|HID0_DCE)@l
+       andi.   0,8,HID0_DCE
+       ori     7,8,HID0_ICFI
+       bne     1f
+       ori     7,7,HID0_DCFI
+1:
+       sync
+       mtspr   SPR_HID0,7
+       sync
+       mtspr   SPR_HID0,8
+       sync
+       isync
 
 /* compute end of kernel memory */
 #if defined(DDB) || NKSYMS || defined(MODULAR)