[src/trunk]: src/sys/arch/arm/broadcom Include the PCI outbound windows in th...

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/9728e5643cbb
branches:  trunk
changeset: 781463:9728e5643cbb
user:      matt <matt%NetBSD.org@localhost>
date:      Fri Sep 07 11:52:30 2012 +0000

description:
Include the PCI outbound windows in the BCM53XX IO space.
Call arml2cc_init from bcm53xx_bootstrap to fill in arm_cache info.

diffstat:

 sys/arch/arm/broadcom/bcm53xx_board.c |  38 +++++++++++++++++-----------------
 sys/arch/arm/broadcom/bcm53xx_reg.h   |  23 ++++++++++++++++++++-
 2 files changed, 41 insertions(+), 20 deletions(-)

diffs (132 lines):

diff -r 2cc4682580b2 -r 9728e5643cbb sys/arch/arm/broadcom/bcm53xx_board.c
--- a/sys/arch/arm/broadcom/bcm53xx_board.c     Fri Sep 07 11:48:59 2012 +0000
+++ b/sys/arch/arm/broadcom/bcm53xx_board.c     Fri Sep 07 11:52:30 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: bcm53xx_board.c,v 1.1 2012/09/01 00:04:44 matt Exp $   */
+/*     $NetBSD: bcm53xx_board.c,v 1.2 2012/09/07 11:52:30 matt Exp $   */
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -34,7 +34,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.1 2012/09/01 00:04:44 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.2 2012/09/07 11:52:30 matt Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -49,6 +49,7 @@
 #define ARMCORE_PRIVATE
 
 #include <arm/cortex/a9tmr_var.h>
+#include <arm/cortex/pl310_var.h>
 #include <arm/mainbus/mainbus.h>
 
 #include <arm/broadcom/bcm53xx_reg.h>
@@ -63,23 +64,20 @@
 static struct bcm53xx_clock_info clk_info;
 
 struct arm32_bus_dma_tag bcm53xx_dma_tag = {
-       0,
-       0,
-       NULL,                   /* _cookie */
-       _bus_dmamap_create,
-       _bus_dmamap_destroy,
-       _bus_dmamap_load,
-       _bus_dmamap_load_mbuf,
-       _bus_dmamap_load_uio,
-       _bus_dmamap_load_raw,
-       _bus_dmamap_unload,
-       _bus_dmamap_sync,
-       NULL,                   /* sync_post */
-       _bus_dmamem_alloc,
-       _bus_dmamem_free,
-       _bus_dmamem_map,
-       _bus_dmamem_unmap,
-       _bus_dmamem_mmap
+       ._dmamap_create = _bus_dmamap_create,
+       ._dmamap_destroy = _bus_dmamap_destroy,
+       ._dmamap_load = _bus_dmamap_load,
+       ._dmamap_load_mbuf = _bus_dmamap_load_mbuf,
+       ._dmamap_load_uio = _bus_dmamap_load_uio,
+       ._dmamap_load_raw = _bus_dmamap_load_raw,
+       ._dmamap_unload = _bus_dmamap_unload,
+       ._dmamap_sync_pre = _bus_dmamap_sync,
+       ._dmamap_sync_post = NULL,
+       ._dmamem_alloc = _bus_dmamem_alloc,
+       ._dmamem_free = _bus_dmamem_free,
+       ._dmamem_map = _bus_dmamem_map,
+       ._dmamem_unmap = _bus_dmamem_unmap,
+       ._dmamem_mmap = _bus_dmamem_mmap
 };
 
 #ifdef BCM53XX_CONSOLE_EARLY
@@ -490,6 +488,8 @@
            bcs.bcs_armcore_clk_pllarmb, bcs.bcs_armcore_clk_policy);
 
        curcpu()->ci_data.cpu_cc_freq = clk->clk_cpu;
+
+       arml2cc_init(bcm53xx_armcore_bst, bcm53xx_armcore_bsh, ARMCORE_L2C_BASE);
 }
 
 #ifdef MULTIPROCESSOR
diff -r 2cc4682580b2 -r 9728e5643cbb sys/arch/arm/broadcom/bcm53xx_reg.h
--- a/sys/arch/arm/broadcom/bcm53xx_reg.h       Fri Sep 07 11:48:59 2012 +0000
+++ b/sys/arch/arm/broadcom/bcm53xx_reg.h       Fri Sep 07 11:52:30 2012 +0000
@@ -45,6 +45,10 @@
  * 0xffff_0000..0xffff_043f    1088B   Internal SKU ROM Region
  * 0xffff_1000..0xffff_1fff       4KB  Enumeration ROM Register Region
  */
+#define        BCM53XX_PCIE0_OWIN_PBASE 0x08000000
+#define        BCM53XX_PCIE0_OWIN_SIZE 0x04000000
+#define        BCM53XX_PCIE0_OWIN_MAX  0x08000000
+
 #define        BCM53XX_IOREG_PBASE     0x18000000
 #define        BCM53XX_IOREG_SIZE      0x00200000
 
@@ -57,7 +61,19 @@
 #define        BCM53XX_SPIFLASH_PBASE  0x1d000000
 #define        BCM53XX_SPIFLASH_SIZE   0x01000000
 
-#define        BCM53XX_IO_SIZE         (BCM53XX_IOREG_SIZE + BCM53XX_ARMCORE_SIZE)
+#define        BCM53XX_PCIE1_OWIN_PBASE 0x40000000
+#define        BCM53XX_PCIE1_OWIN_SIZE 0x04000000
+#define        BCM53XX_PCIE1_OWIN_MAX  0x08000000
+
+#define        BCM53XX_PCIE2_OWIN_PBASE 0x48000000
+#define        BCM53XX_PCIE2_OWIN_SIZE 0x04000000
+#define        BCM53XX_PCIE2_OWIN_MAX  0x08000000
+
+#define        BCM53XX_IO_SIZE         (BCM53XX_IOREG_SIZE             \
+                                + BCM53XX_ARMCORE_SIZE         \
+                                + BCM53XX_PCIE0_OWIN_SIZE      \
+                                + BCM53XX_PCIE1_OWIN_SIZE      \
+                                + BCM53XX_PCIE2_OWIN_SIZE)
 
 #define        BCM53XX_REF_CLK         (25*1000*1000)
 
@@ -437,11 +453,15 @@
 #define        PCIE_OARR_0             0xd20
 #define        PCIE_OARR_1             0xd28
 
+#define  PCIE_OARR_ADDR                __BITS(31,26)
+
 #define        PCIE_OMAP_0_LOWER       0xd40
 #define        PCIE_OMAP_0_UPPER       0xd44
 #define        PCIE_OMAP_1_LOWER       0xd48
 #define        PCIE_OMAP_1_UPPER       0xd4c
 
+#define  PCIE_OMAP_ADDRL       __BITS(31,26)
+
 #define        PCIE_FUNC1_IARR_1_SIZE  0xd58
 #define        PCIE_FUNC1_IARR_2_SIZE  0xd5c
 
@@ -517,6 +537,7 @@
 #endif /* PCIE_PRIVATE */
 
 #define        ARMCORE_SCU_BASE        0x20000         /* CBAR is 19020000 */
+#define        ARMCORE_L2C_BASE        0x22000
 
 #ifdef ARMCORE_PRIVATE