[src/trunk]: src/sys/arch/arm/include Add more c7 register inlines. Add some...

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/cddf3a3d8096
branches:  trunk
changeset: 781504:cddf3a3d8096
user:      matt <matt%NetBSD.org@localhost>
date:      Tue Sep 11 15:31:54 2012 +0000

description:
Add more c7 register inlines.  Add some more CT4 defintions

diffstat:

 sys/arch/arm/include/armreg.h |  24 +++++++++++++++++++++++-
 1 files changed, 23 insertions(+), 1 deletions(-)

diffs (46 lines):

diff -r 9e7b0558c33e -r cddf3a3d8096 sys/arch/arm/include/armreg.h
--- a/sys/arch/arm/include/armreg.h     Tue Sep 11 15:28:14 2012 +0000
+++ b/sys/arch/arm/include/armreg.h     Tue Sep 11 15:31:54 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: armreg.h,v 1.64 2012/09/07 11:48:59 matt Exp $ */
+/*     $NetBSD: armreg.h,v 1.65 2012/09/11 15:31:54 matt Exp $ */
 
 /*
  * Copyright (c) 1998, 2001 Ben Harris
@@ -416,7 +416,11 @@
 #define        CPU_CT4_ILINE(x)        ((x) & 0xf)             /* I$ line size */
 #define        CPU_CT4_DLINE(x)        (((x) >> 16) & 0xf)     /* D$ line size */
 #define        CPU_CT4_L1IPOLICY(x)    (((x) >> 14) & 0x3)     /* I$ policy */
+#define        CPU_CT4_L1_AIVIVT       1                       /* ASID tagged VIVT */
 #define        CPU_CT4_L1_VIPT         2                       /* VIPT */
+#define        CPU_CT4_L1_PIPT         3                       /* PIPT */
+#define        CPU_CT4_ERG(x)          (((x) >> 20) & 0xf)     /* Cache WriteBack Granule */
+#define        CPU_CT4_CWG(x)          (((x) >> 24) & 0xf)     /* Exclusive Resv. Granule */
 
 /* Cache size identifaction register definitions 1, Rd, c0, c0, 0 */
 #define        CPU_CSID_CTYPE_WT       0x80000000      /* write-through avail */ 
@@ -572,6 +576,24 @@
 ARMREG_WRITE_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */
 ARMREG_READ_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
 ARMREG_WRITE_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
+/* c7 registers */
+ARMREG_WRITE_INLINE(icialluis, "p15,0,%0,c7,c1,0") /* Instruction Inv All (IS) */
+ARMREG_WRITE_INLINE(bpiallis, "p15,0,%0,c7,c1,6") /* Branch Invalidate All (IS) */
+ARMREG_READ_INLINE(par, "p15,0,%0,c7,c4,0") /* Physical Address Register */
+ARMREG_WRITE_INLINE(iciallu, "p15,0,%0,c7,c5,0") /* Instruction Invalidate All */
+ARMREG_WRITE_INLINE(icimvau, "p15,0,%0,c7,c5,1") /* Instruction Invalidate MVA */
+ARMREG_WRITE_INLINE(isb, "p15,0,%0,c7,c5,4") /* Instruction Synchronization Barrier */
+ARMREG_WRITE_INLINE(bpiall, "p15,0,%0,c5,c1,6") /* Breakpoint Invalidate All */
+ARMREG_WRITE_INLINE(dcimvac, "p15,0,%0,c7,c6,1") /* Data Invalidate MVA to PoC */
+ARMREG_WRITE_INLINE(dcisw, "p15,0,%0,c7,c6,2") /* Data Invalidate Set/Way */
+ARMREG_WRITE_INLINE(ats1cpr, "p15,0,%0,c7,c8,0") /* AddrTrans CurState PL1 Read */
+ARMREG_WRITE_INLINE(dccmvac, "p15,0,%0,c7,c10,1") /* Data Clean MVA to PoC */
+ARMREG_WRITE_INLINE(dccsw, "p15,0,%0,c7,c10,2") /* Data Clean Set/Way */
+ARMREG_WRITE_INLINE(dsb, "p15,0,%0,c7,c10,4") /* Data Synchronization Barrier */
+ARMREG_WRITE_INLINE(dmb, "p15,0,%0,c7,c10,5") /* Data Memory Barrier */
+ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c14,1") /* Data Clean MVA to PoU */
+ARMREG_WRITE_INLINE(dccimvac, "p15,0,%0,c7,c14,1") /* Data Clean&Inv MVA to PoC */
+ARMREG_WRITE_INLINE(dccisw, "p15,0,%0,c7,c14,2") /* Data Clean&Inv Set/Way */
 /* c9 registers */
 ARMREG_READ_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */
 ARMREG_WRITE_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */