[src/netbsd-6]: src/sys/arch/arm/marvell Pull up following revision(s) (reque...

[riz <riz%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/b14ce77ec7f3
branches:  netbsd-6
changeset: 775388:b14ce77ec7f3
user:      riz <riz%NetBSD.org@localhost>
date:      Tue Oct 23 19:50:49 2012 +0000

description:
Pull up following revision(s) (requested by msaitoh in ticket #623):
        sys/arch/arm/marvell/mvsocgpp.c: revision 1.4
Fix a bug that the irq_masks of GPIO are set on Marvell SoCs.

diffstat:

 sys/arch/arm/marvell/mvsocgpp.c |  11 ++++++++---
 1 files changed, 8 insertions(+), 3 deletions(-)

diffs (62 lines):

diff -r c5192f0f7320 -r b14ce77ec7f3 sys/arch/arm/marvell/mvsocgpp.c
--- a/sys/arch/arm/marvell/mvsocgpp.c   Tue Oct 23 19:48:25 2012 +0000
+++ b/sys/arch/arm/marvell/mvsocgpp.c   Tue Oct 23 19:50:49 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mvsocgpp.c,v 1.3 2011/08/13 15:38:47 jakllsch Exp $    */
+/*     $NetBSD: mvsocgpp.c,v 1.3.8.1 2012/10/23 19:50:49 riz Exp $     */
 /*
  * Copyright (c) 2008, 2010 KIYOHARA Takashi
  * All rights reserved.
@@ -26,7 +26,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mvsocgpp.c,v 1.3 2011/08/13 15:38:47 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mvsocgpp.c,v 1.3.8.1 2012/10/23 19:50:49 riz Exp $");
 
 #include "gpio.h"
 
@@ -71,6 +71,7 @@
        struct mvsocgpp_pic {
                struct pic_softc gpio_pic;
                int group;
+               int shift;
                uint32_t edge;
                uint32_t level;
        } *sc_pic;
@@ -183,6 +184,7 @@
                aprint_normal(", intr %d\n", mva->mva_irq + j);
 
                (sc->sc_pic + j)->group = j;
+               (sc->sc_pic + j)->shift = (j & 3) * 8;
        }
 
 #ifdef MVSOCGPP_DUMPREG
@@ -244,6 +246,7 @@
        uint32_t mask;
        int pin = mvsocgpp_pic->group << 3;
 
+       irq_mask = irq_mask << mvsocgpp_pic->shift;
        MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIC(pin),
            MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(pin)) & ~irq_mask);
        if (irq_mask & mvsocgpp_pic->edge) {
@@ -266,6 +269,7 @@
        struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic;
        int pin = mvsocgpp_pic->group << 3;
 
+       irq_mask = irq_mask << mvsocgpp_pic->shift;
        MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin),
            MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)) & ~irq_mask);
        MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin),
@@ -281,9 +285,10 @@
        int pin = mvsocgpp_pic->group << 3;
 
        pending = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(pin));
-       pending &= (0xff << mvsocgpp_pic->group);
+       pending &= (0xff << mvsocgpp_pic->shift);
        pending &= (MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)) |
                    MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin)));
+       pending = pending >> mvsocgpp_pic->shift;
 
        if (pending == 0)
                return 0;