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[src/netbsd-6]: src Pull up revisions:
details: https://anonhg.NetBSD.org/src/rev/a003cb5f3fbd
branches: netbsd-6
changeset: 774394:a003cb5f3fbd
user: jdc <jdc%NetBSD.org@localhost>
date: Thu Aug 09 06:36:42 2012 +0000
description:
Pull up revisions:
src/sys/arch/evbarm/dev/plcomreg.h revisions 1.2,1.3,1.4
src/sys/arch/evbarm/conf/INTEGRATOR revision 1.65
src/sys/arch/evbarm/dev/plcom.c revisions 1.34,1.35,1.36,1.37,1.38,1.39,1.40
src/sys/arch/evbarm/ifpga/plcom_ifpga.c revisions 1.12,1.13,1.14
src/sys/arch/evbarm/dev/plcomvar.h revisions 1.9,1.10,1.11
src/sys/arch/evbarm/ifpga/plcom_ifpgavar.h revision 1.2
src/sys/arch/arm/arm/cpufunc.c revisions 1.105,1.108
src/sys/arch/arm/arm32/cpu.c revision 1.79
src/sys/arch/arm/include/armreg.h revisions 1.49,1.54
src/sys/arch/arm/arm32/pmap.c revision 1.229
src/sys/arch/arm/arm32/arm32_machdep.c revision 1.77
src/sys/arch/arm/include/cpu.h revision 1.64
src/sys/arch/arm/arm/cpufunc_asm_arm1136.S revision 1.3
src/sys/arch/arm/arm/cpufunc_asm_arm11x6.S revision 1.1
src/sys/arch/arm/conf/files.arm revision 1.106
src/sys/arch/arm/include/cpufunc.h revision 1.57
src/sys/dev/sdmmc/sdhc.c revisions 1.14,1.24
src/sys/dev/sdmmc/sdhcvar.h revisions 1.7,1.8
src/sys/arch/evbarm/ifpga/ifpgareg.h revision 1.4
src/sys/arch/evbarm/integrator/integrator_machdep.c revision 1.69
src/sys/arch/arm/broadcom/bcm2835_dma.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_emmc.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_intr.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_intr.h revision 1.1
src/sys/arch/arm/broadcom/bcm2835_obio.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_plcom.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_pm.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_pmvar.h revision 1.1
src/sys/arch/arm/broadcom/bcm2835_space.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835_tmr.c revision 1.1
src/sys/arch/arm/broadcom/bcm2835reg.h revision 1.1
src/sys/arch/arm/broadcom/bcm2835var.h revision 1.1
src/sys/arch/arm/broadcom/bcm_amba.h revision 1.1
src/sys/arch/arm/broadcom/files.bcm2835 revision 1.1
src/sys/arch/evbarm/Makefile revision 1.9
src/sys/arch/evbarm/conf/RPI revision 1.1
src/sys/arch/evbarm/conf/files.rpi revision 1.1
src/sys/arch/evbarm/conf/mk.rpi revision 1.1
src/sys/arch/evbarm/conf/std.rpi revision 1.1
src/sys/arch/evbarm/rpi/genassym.cf revision 1.1
src/sys/arch/evbarm/rpi/rpi.h revision 1.1
src/sys/arch/evbarm/rpi/rpi_machdep.c revision 1.1
src/sys/arch/evbarm/rpi/rpi_start.S revision 1.1,1.2
src/etc/etc.evbarm/Makefile.inc revision 1.28
(requested by skrll in ticket #454).
don't mix #define<TAB> and #define<SPACE> in a file.
avoid warning with options PLCOM_DEBUG for INTEGRATOR.
Rename register values. No functional change - same code before and after.
Existing names are prefixed with PL01X_ where they're common between the
PL010 and the PL011. The PL010_/PL011_ prefixes are added where they're
found only on the respective chips.
Replace the simple_lock with a kmutex_t. Update the locking to match
com(4) in the few places it didn't already.
DOH. Replace a line that got accidently deleted in the last commit.
device_t/softc split
struct device * -> device_t
struct cfdata * -> cfdata_t
Add the 'Z' to the 1176 cpu product name.
ok matt@
Fix locking botch introduced in 1.36.
Fix a KASSERT. From/OK'ed by matt@
Fix racy softint dispatch that lead to KASSERT(si->si_active) in
softint_execute
Discussed with matt@. "Looks good to me"
Add the documented ARM11[37]6 Auxiliary control register defines.
Add support for the ARM1176JZS
Add a flag for the lack of LED_ON in HOST_CTL (ti omap3 doesn't do that).
Provide a method for attachments to specify capabilites.
Add support for the PL011 to plcom. Pull across a bunch of fixes from
com(4) while I'm here and do some other tidyup.
Tested on a RaspberryPi.
PL010 not tested.
Initial commit of support for the RaspberryPI (www.raspberrypi.org)
This is enough for serial console via the gpio header pins and to get to
multiuser.
A huge thank you to Matt Thomas for all his help.
Add RPI to KERNEL_SETS
Remove #if 0 code.
diffstat:
etc/etc.evbarm/Makefile.inc | 4 +-
sys/arch/arm/arm/cpufunc.c | 119 ++-
sys/arch/arm/arm/cpufunc_asm_arm1136.S | 128 +--
sys/arch/arm/arm/cpufunc_asm_arm11x6.S | 219 ++++
sys/arch/arm/arm32/arm32_machdep.c | 17 +-
sys/arch/arm/arm32/cpu.c | 6 +-
sys/arch/arm/arm32/pmap.c | 6 +-
sys/arch/arm/broadcom/bcm2835_dma.c | 61 +
sys/arch/arm/broadcom/bcm2835_emmc.c | 130 ++
sys/arch/arm/broadcom/bcm2835_intr.c | 250 +++++
sys/arch/arm/broadcom/bcm2835_intr.h | 55 +
sys/arch/arm/broadcom/bcm2835_obio.c | 197 ++++
sys/arch/arm/broadcom/bcm2835_plcom.c | 98 ++
sys/arch/arm/broadcom/bcm2835_pm.c | 125 ++
sys/arch/arm/broadcom/bcm2835_pmvar.h | 37 +
sys/arch/arm/broadcom/bcm2835_space.c | 391 ++++++++
sys/arch/arm/broadcom/bcm2835_tmr.c | 231 +++++
sys/arch/arm/broadcom/bcm2835reg.h | 115 ++
sys/arch/arm/broadcom/bcm2835var.h | 44 +
sys/arch/arm/broadcom/bcm_amba.h | 29 +
sys/arch/arm/broadcom/files.bcm2835 | 46 +
sys/arch/arm/conf/files.arm | 3 +-
sys/arch/arm/include/armreg.h | 19 +-
sys/arch/arm/include/cpu.h | 2 +-
sys/arch/arm/include/cpufunc.h | 19 +-
sys/arch/evbarm/Makefile | 4 +-
sys/arch/evbarm/conf/INTEGRATOR | 3 +-
sys/arch/evbarm/conf/RPI | 242 +++++
sys/arch/evbarm/conf/files.rpi | 13 +
sys/arch/evbarm/conf/mk.rpi | 17 +
sys/arch/evbarm/conf/std.rpi | 25 +
sys/arch/evbarm/dev/plcom.c | 1008 +++++++++++++++-------
sys/arch/evbarm/dev/plcomreg.h | 164 ++-
sys/arch/evbarm/dev/plcomvar.h | 62 +-
sys/arch/evbarm/ifpga/ifpgareg.h | 3 +-
sys/arch/evbarm/ifpga/plcom_ifpga.c | 44 +-
sys/arch/evbarm/ifpga/plcom_ifpgavar.h | 5 +-
sys/arch/evbarm/integrator/integrator_machdep.c | 60 +-
sys/arch/evbarm/rpi/genassym.cf | 36 +
sys/arch/evbarm/rpi/rpi.h | 50 +
sys/arch/evbarm/rpi/rpi_machdep.c | 829 ++++++++++++++++++
sys/arch/evbarm/rpi/rpi_start.S | 321 +++++++
sys/dev/sdmmc/sdhc.c | 17 +-
sys/dev/sdmmc/sdhcvar.h | 6 +-
44 files changed, 4628 insertions(+), 632 deletions(-)
diffs (truncated from 6875 to 300 lines):
diff -r 6f6302568412 -r a003cb5f3fbd etc/etc.evbarm/Makefile.inc
--- a/etc/etc.evbarm/Makefile.inc Wed Aug 08 15:58:17 2012 +0000
+++ b/etc/etc.evbarm/Makefile.inc Thu Aug 09 06:36:42 2012 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.inc,v 1.27 2012/02/14 15:09:02 jakllsch Exp $
+# $NetBSD: Makefile.inc,v 1.27.2.1 2012/08/09 06:36:51 jdc Exp $
#
# etc.evbarm/Makefile.inc -- evbarm-specific etc Makefile targets
#
@@ -23,7 +23,7 @@
.if ${MACHINE_ARCH} == "arm"
# Little endian platforms.
-KERNEL_SETS+= IXM1200 HDL_G
+KERNEL_SETS+= IXM1200 HDL_G RPI
.else
# Big endian platforms.
KERNEL_SETS+= IXM1200 NSLU2
diff -r 6f6302568412 -r a003cb5f3fbd sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c Wed Aug 08 15:58:17 2012 +0000
+++ b/sys/arch/arm/arm/cpufunc.c Thu Aug 09 06:36:42 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.104 2012/01/31 04:31:37 matt Exp $ */
+/* $NetBSD: cpufunc.c,v 1.104.2.1 2012/08/09 06:36:44 jdc Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.104 2012/01/31 04:31:37 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.104.2.1 2012/08/09 06:36:44 jdc Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -747,7 +747,7 @@
.cf_control = cpufunc_control,
.cf_domains = cpufunc_domains,
- .cf_setttb = arm1136_setttb,
+ .cf_setttb = arm11x6_setttb,
.cf_faultstatus = cpufunc_faultstatus,
.cf_faultaddress = cpufunc_faultaddress,
@@ -762,25 +762,25 @@
/* Cache operations */
- .cf_icache_sync_all = arm1136_icache_sync_all, /* 411920 */
- .cf_icache_sync_range = arm1136_icache_sync_range, /* 371025 */
-
- .cf_dcache_wbinv_all = arm1136_dcache_wbinv_all, /* 411920 */
+ .cf_icache_sync_all = arm11x6_icache_sync_all, /* 411920 */
+ .cf_icache_sync_range = arm11x6_icache_sync_range, /* 371025 */
+
+ .cf_dcache_wbinv_all = arm11x6_dcache_wbinv_all, /* 411920 */
.cf_dcache_wbinv_range = armv6_dcache_wbinv_range,
.cf_dcache_inv_range = armv6_dcache_inv_range,
.cf_dcache_wb_range = armv6_dcache_wb_range,
- .cf_idcache_wbinv_all = arm1136_idcache_wbinv_all, /* 411920 */
- .cf_idcache_wbinv_range = arm1136_idcache_wbinv_range, /* 371025 */
+ .cf_idcache_wbinv_all = arm11x6_idcache_wbinv_all, /* 411920 */
+ .cf_idcache_wbinv_range = arm11x6_idcache_wbinv_range, /* 371025 */
/* Other functions */
- .cf_flush_prefetchbuf = arm1136_flush_prefetchbuf,
+ .cf_flush_prefetchbuf = arm11x6_flush_prefetchbuf,
.cf_drain_writebuf = arm11_drain_writebuf,
.cf_flush_brnchtgt_C = cpufunc_nullop,
.cf_flush_brnchtgt_E = (void *)cpufunc_nullop,
- .cf_sleep = arm11_sleep,
+ .cf_sleep = arm11_sleep, /* arm1136_sleep_rev0 */
/* Soft functions */
@@ -789,11 +789,70 @@
.cf_context_switch = arm11_context_switch,
- .cf_setup = arm1136_setup
+ .cf_setup = arm11x6_setup
};
#endif /* CPU_ARM1136 */
+#ifdef CPU_ARM1176
+struct cpu_functions arm1176_cpufuncs = {
+ /* CPU functions */
+
+ .cf_id = cpufunc_id,
+ .cf_cpwait = cpufunc_nullop,
+
+ /* MMU functions */
+
+ .cf_control = cpufunc_control,
+ .cf_domains = cpufunc_domains,
+ .cf_setttb = arm11x6_setttb,
+ .cf_faultstatus = cpufunc_faultstatus,
+ .cf_faultaddress = cpufunc_faultaddress,
+
+ /* TLB functions */
+
+ .cf_tlb_flushID = arm11_tlb_flushID,
+ .cf_tlb_flushID_SE = arm11_tlb_flushID_SE,
+ .cf_tlb_flushI = arm11_tlb_flushI,
+ .cf_tlb_flushI_SE = arm11_tlb_flushI_SE,
+ .cf_tlb_flushD = arm11_tlb_flushD,
+ .cf_tlb_flushD_SE = arm11_tlb_flushD_SE,
+
+ /* Cache operations */
+
+ .cf_icache_sync_all = arm11x6_icache_sync_all, /* 415045 */
+ .cf_icache_sync_range = arm11x6_icache_sync_range, /* 371367 */
+
+ .cf_dcache_wbinv_all = arm11x6_dcache_wbinv_all, /* 415045 */
+ .cf_dcache_wbinv_range = armv6_dcache_wbinv_range,
+ .cf_dcache_inv_range = armv6_dcache_inv_range,
+ .cf_dcache_wb_range = armv6_dcache_wb_range,
+
+ .cf_idcache_wbinv_all = arm11x6_idcache_wbinv_all, /* 415045 */
+ .cf_idcache_wbinv_range = arm11x6_idcache_wbinv_range, /* 371367 */
+
+ /* Other functions */
+
+ .cf_flush_prefetchbuf = arm11x6_flush_prefetchbuf,
+ .cf_drain_writebuf = arm11_drain_writebuf,
+ .cf_flush_brnchtgt_C = cpufunc_nullop,
+ .cf_flush_brnchtgt_E = (void *)cpufunc_nullop,
+
+ .cf_sleep = arm11x6_sleep, /* no ref. */
+
+ /* Soft functions */
+
+ .cf_dataabt_fixup = cpufunc_null_fixup,
+ .cf_prefetchabt_fixup = cpufunc_null_fixup,
+
+ .cf_context_switch = arm11_context_switch,
+
+ .cf_setup = arm11x6_setup
+
+};
+#endif /* CPU_ARM1176 */
+
+
#ifdef CPU_ARM11MPCORE
struct cpu_functions arm11mpcore_cpufuncs = {
/* CPU functions */
@@ -1646,15 +1705,21 @@
#if defined(CPU_ARM11)
if (cputype == CPU_ID_ARM1136JS ||
cputype == CPU_ID_ARM1136JSR1 ||
- cputype == CPU_ID_ARM1176JS) {
+ cputype == CPU_ID_ARM1176JZS) {
cpufuncs = arm11_cpufuncs;
#if defined(CPU_ARM1136)
- if (cputype != CPU_ID_ARM1176JS) {
+ if (cputype == CPU_ID_ARM1136JS &&
+ cputype == CPU_ID_ARM1136JSR1) {
cpufuncs = arm1136_cpufuncs;
if (cputype == CPU_ID_ARM1136JS)
cpufuncs.cf_sleep = arm1136_sleep_rev0;
}
#endif
+#if defined(CPU_ARM1176)
+ if (cputype == CPU_ID_ARM1176JZS) {
+ cpufuncs = arm1176_cpufuncs;
+ }
+#endif
cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
cpu_do_powersave = 1; /* Enable powersave */
get_cachetype_cp15();
@@ -2251,7 +2316,7 @@
defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
- defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_ARM1136) || \
+ defined(CPU_ARM10) || defined(CPU_ARM11) || \
defined(CPU_FA526) || defined(CPU_CORTEX) || defined(CPU_SHEEVA)
#define IGN 0
@@ -2862,10 +2927,9 @@
#endif /* CPU_CORTEX */
-
-#if defined(CPU_ARM1136)
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
void
-arm1136_setup(char *args)
+arm11x6_setup(char *args)
{
int cpuctrl, cpuctrl_wax;
uint32_t auxctrl, auxctrl_wax;
@@ -2920,7 +2984,8 @@
auxctrl = 0;
auxctrl_wax = ~0;
- /* This options enables the workaround for the 364296 ARM1136
+ /*
+ * This options enables the workaround for the 364296 ARM1136
* r0pX errata (possible cache data corruption with
* hit-under-miss enabled). It sets the undocumented bit 31 in
* the auxiliary control register and the FI bit in the control
@@ -2934,6 +2999,14 @@
auxctrl_wax = ~ARM11R0_AUXCTL_PFI;
}
+ /*
+ * Enable an errata workaround
+ */
+ if ((cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM1176JZS) { /* ARM1176JZSr0 */
+ auxctrl = ARM1176_AUXCTL_PHD;
+ auxctrl_wax = ~ARM1176_AUXCTL_PHD;
+ }
+
/* Clear out the cache */
cpu_idcache_wbinv_all();
@@ -2948,17 +3021,17 @@
cpu_control(~cpuctrl_wax, cpuctrl);
__asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t"
- "bic %1, %0, %2\n\t"
- "eor %1, %0, %3\n\t"
+ "and %1, %0, %2\n\t"
+ "orr %1, %1, %3\n\t"
"teq %0, %1\n\t"
"mcrne p15, 0, %1, c1, c0, 1\n\t"
: "=r"(tmp), "=r"(tmp2) :
- "r"(~auxctrl_wax), "r"(auxctrl));
+ "r"(auxctrl_wax), "r"(auxctrl));
/* And again. */
cpu_idcache_wbinv_all();
}
-#endif /* CPU_ARM1136 */
+#endif /* CPU_ARM1136 || CPU_ARM1176 */
#ifdef CPU_SA110
struct cpu_option sa110_options[] = {
diff -r 6f6302568412 -r a003cb5f3fbd sys/arch/arm/arm/cpufunc_asm_arm1136.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm1136.S Wed Aug 08 15:58:17 2012 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm1136.S Thu Aug 09 06:36:42 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm1136.S,v 1.2 2008/04/27 18:58:43 matt Exp $ */
+/* $NetBSD: cpufunc_asm_arm1136.S,v 1.2.40.1 2012/08/09 06:36:45 jdc Exp $ */
/*
* Copyright (c) 2007 Microsoft
@@ -33,131 +33,7 @@
#include <machine/cpu.h>
#include <machine/asm.h>
-RCSID("$NetBSD: cpufunc_asm_arm1136.S,v 1.2 2008/04/27 18:58:43 matt Exp $")
-
-#if 0
-#define Invalidate_I_cache(Rtmp1, Rtmp2) \
- mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */
-#else
-/*
- * Workaround Erratum 411920
- *
- * - value of arg 'reg' Should Be Zero
- */
-#define Invalidate_I_cache(Rtmp1, Rtmp2) \
- mov Rtmp1, #0; /* SBZ */ \
- mrs Rtmp2, cpsr; \
- cpsid ifa; \
- mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
- mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
- mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
- mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
- msr cpsr_cx, Rtmp2; \
- nop; \
- nop; \
- nop; \
- nop; \
- nop; \
- nop; \
- nop; \
- nop; \
- nop; \
- nop; \
- nop;
-#endif
-
-#if 1
-#define Flush_D_cache(reg) \
- mov reg, #0; /* SBZ */ \
- mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
- mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
-#else
-#define Flush_D_cache(reg) \
-1: mov reg, #0; /* SBZ */ \
- mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
- mrc p15, 0, reg, C7, C10, 6;/* Read Cache Dirty Status Register */ \
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