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[src/trunk]: src/sys/dev/marvell Support Kirkwoods. Kirkwoods has 4ch for XO...
details: https://anonhg.NetBSD.org/src/rev/75dd6e5cba27
branches: trunk
changeset: 780427:75dd6e5cba27
user: kiyohara <kiyohara%NetBSD.org@localhost>
date: Mon Jul 23 06:09:47 2012 +0000
description:
Support Kirkwoods. Kirkwoods has 4ch for XORE and not has IDMAC. tested on OpenBlockS A6 with ch0 only.
diffstat:
sys/dev/marvell/gtidmac.c | 728 +++++++++++++++++++++++++-----------------
sys/dev/marvell/gtidmacreg.h | 74 ++-
2 files changed, 485 insertions(+), 317 deletions(-)
diffs (truncated from 1085 to 300 lines):
diff -r 26c9f4f541cf -r 75dd6e5cba27 sys/dev/marvell/gtidmac.c
--- a/sys/dev/marvell/gtidmac.c Mon Jul 23 04:25:03 2012 +0000
+++ b/sys/dev/marvell/gtidmac.c Mon Jul 23 06:09:47 2012 +0000
@@ -1,6 +1,6 @@
-/* $NetBSD: gtidmac.c,v 1.7 2012/01/30 23:31:28 matt Exp $ */
+/* $NetBSD: gtidmac.c,v 1.8 2012/07/23 06:09:47 kiyohara Exp $ */
/*
- * Copyright (c) 2008 KIYOHARA Takashi
+ * Copyright (c) 2008, 2012 KIYOHARA Takashi
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gtidmac.c,v 1.7 2012/01/30 23:31:28 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gtidmac.c,v 1.8 2012/07/23 06:09:47 kiyohara Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -147,7 +147,9 @@
static void gtidmac_attach(device_t, device_t, void *);
static int gtidmac_intr(void *);
-static int mvxore_intr(void *);
+static int mvxore_port0_intr(void *);
+static int mvxore_port1_intr(void *);
+static int mvxore_intr(struct gtidmac_softc *, int);
static void gtidmac_process(struct dmover_backend *);
static void gtidmac_dmover_run(struct dmover_backend *);
@@ -163,6 +165,9 @@
static void gtidmac_wininit(struct gtidmac_softc *);
static void mvxore_wininit(struct gtidmac_softc *);
+static int gtidmac_buffer_setup(struct gtidmac_softc *);
+static int mvxore_buffer_setup(struct gtidmac_softc *);
+
#ifdef GTIDMAC_DEBUG
static void gtidmac_dump_idmacreg(struct gtidmac_softc *, int);
static void gtidmac_dump_idmacdesc(struct gtidmac_softc *,
@@ -271,6 +276,45 @@
},
};
+static struct {
+ int model;
+ int idmac_nchan;
+ int idmac_irq;
+ int xore_nchan;
+ int xore_irq;
+} channels[] = {
+ /*
+ * Marvell System Controllers:
+ * need irqs in attach_args.
+ */
+ { MARVELL_DISCOVERY, 8, -1, 0, -1 },
+ { MARVELL_DISCOVERY_II, 8, -1, 0, -1 },
+ { MARVELL_DISCOVERY_III, 8, -1, 0, -1 },
+#if 0
+ { MARVELL_DISCOVERY_LT, 4, -1, 2, -1 },
+ { MARVELL_DISCOVERY_V, 4, -1, 2, -1 },
+ { MARVELL_DISCOVERY_VI, 4, -1, 2, -1 }, ????
+#endif
+
+ /*
+ * Marvell System on Chips:
+ * No need irqs in attach_args. We always connecting to interrupt-pin
+ * statically.
+ */
+ { MARVELL_ORION_1_88F1181, 4, 24, 0, -1 },
+ { MARVELL_ORION_2_88F1281, 4, 24, 0, -1 },
+ { MARVELL_ORION_1_88F5082, 4, 24, 0, -1 },
+ { MARVELL_ORION_1_88F5180N, 4, 24, 0, -1 },
+ { MARVELL_ORION_1_88F5181, 4, 24, 0, -1 },
+ { MARVELL_ORION_1_88F5182, 4, 24, 2, 30 },
+ { MARVELL_ORION_2_88F5281, 4, 24, 0, -1 },
+ { MARVELL_ORION_1_88W8660, 4, 24, 0, -1 },
+ { MARVELL_KIRKWOOD_88F6180, 0, -1, 4, 5 },
+ { MARVELL_KIRKWOOD_88F6192, 0, -1, 4, 5 },
+ { MARVELL_KIRKWOOD_88F6281, 0, -1, 4, 5 },
+ { MARVELL_KIRKWOOD_88F6282, 0, -1, 4, 5 },
+};
+
CFATTACH_DECL_NEW(gtidmac_gt, sizeof(struct gtidmac_softc),
gtidmac_match, gtidmac_attach, NULL, NULL);
CFATTACH_DECL_NEW(gtidmac_mbus, sizeof(struct gtidmac_softc),
@@ -282,15 +326,18 @@
gtidmac_match(device_t parent, struct cfdata *match, void *aux)
{
struct marvell_attach_args *mva = aux;
+ int i;
if (strcmp(mva->mva_name, match->cf_name) != 0)
return 0;
- if (mva->mva_offset == MVA_OFFSET_DEFAULT ||
- mva->mva_irq == MVA_IRQ_DEFAULT)
+ if (mva->mva_offset == MVA_OFFSET_DEFAULT)
return 0;
-
- mva->mva_size = GTIDMAC_SIZE;
- return 1;
+ for (i = 0; i < __arraycount(channels); i++)
+ if (mva->mva_model == channels[i].model) {
+ mva->mva_size = GTIDMAC_SIZE;
+ return 1;
+ }
+ return 0;
}
/* ARGSUSED */
@@ -299,51 +346,51 @@
{
struct gtidmac_softc *sc = device_private(self);
struct marvell_attach_args *mva = aux;
- bus_dma_segment_t segs, segs_xore;
- struct gtidmac_dma_desc *dd;
prop_dictionary_t dict = device_properties(self);
- uint32_t mask, dmb_speed, xore_irq;
- int idmac_nchan, xore_nchan, nsegs, nsegs_xore, i, j, k, n;
-
- xore_irq = 0;
- idmac_nchan = 8;
- xore_nchan = 0;
- switch (mva->mva_model) {
- case MARVELL_DISCOVERY:
- case MARVELL_DISCOVERY_II:
- case MARVELL_DISCOVERY_III:
- break;
+ uint32_t idmac_irq, xore_irq, dmb_speed;
+ int idmac_nchan, xore_nchan, nsegs, i, j, n;
- case MARVELL_ORION_1_88F1181:
- case MARVELL_ORION_1_88F5082:
- case MARVELL_ORION_1_88F5180N:
- case MARVELL_ORION_1_88F5181:
- case MARVELL_ORION_1_88W8660:
- case MARVELL_ORION_2_88F1281:
- case MARVELL_ORION_2_88F5281:
- idmac_nchan = 4;
- break;
-
-#if 0
- case MARVELL_DISCOVERY_LT:
- case MARVELL_DISCOVERY_V:
- case MARVELL_DISCOVERY_VI: ????
-#endif
- case MARVELL_ORION_1_88F5182:
- idmac_nchan = 4;
- xore_nchan = 2;
- break;
+ for (i = 0; i < __arraycount(channels); i++)
+ if (mva->mva_model == channels[i].model)
+ break;
+ idmac_nchan = channels[i].idmac_nchan;
+ idmac_irq = channels[i].idmac_irq;
+ if (idmac_nchan != 0) {
+ if (idmac_irq == -1)
+ idmac_irq = mva->mva_irq;
+ if (idmac_irq == -1)
+ /* Discovery */
+ if (!prop_dictionary_get_uint32(dict,
+ "idmac-irq", &idmac_irq)) {
+ aprint_error(": no idmac-irq property\n");
+ return;
+ }
}
- if (xore_nchan != 0)
- if (!prop_dictionary_get_uint32(dict, "xore-irq-begin",
- &xore_irq)) {
- aprint_error(": no xore-irq-begin property\n");
- return;
- }
+ xore_nchan = channels[i].xore_nchan;
+ xore_irq = channels[i].xore_irq;
+ if (xore_nchan != 0) {
+ if (xore_irq == -1)
+ xore_irq = mva->mva_irq;
+ if (xore_irq == -1)
+ /* Discovery LT/V/VI */
+ if (!prop_dictionary_get_uint32(dict,
+ "xore-irq", &xore_irq)) {
+ aprint_error(": no xore-irq property\n");
+ return;
+ }
+ }
aprint_naive("\n");
aprint_normal(": Marvell IDMA Controller%s\n",
xore_nchan ? "/XOR Engine" : "");
+ if (idmac_nchan > 0)
+ aprint_normal_dev(self,
+ "IDMA Controller %d channels, intr %d...%d\n",
+ idmac_nchan, idmac_irq, idmac_irq + GTIDMAC_NINTRRUPT - 1);
+ if (xore_nchan > 0)
+ aprint_normal_dev(self,
+ "XOR Engine %d channels, intr %d...%d\n",
+ xore_nchan, xore_irq, xore_irq + xore_nchan - 1);
sc->sc_dev = self;
sc->sc_iot = mva->mva_iot;
@@ -383,198 +430,54 @@
for (j = 0; j < sizeof(sc->sc_pbuf[i].pbuf); j++)
sc->sc_pbuf[i].pbuf[j] = i;
- /* IDMAC DMA descriptor buffer */
- sc->sc_gtidmac_nchan = idmac_nchan;
- if (bus_dmamem_alloc(sc->sc_dmat,
- sizeof(struct gtidmac_desc) * GTIDMAC_NDESC * idmac_nchan,
- PAGE_SIZE, 0, &segs, 1, &nsegs, BUS_DMA_NOWAIT)) {
- aprint_error_dev(self,
- "bus_dmamem_alloc failed: descriptor buffer\n");
- goto fail4;
- }
- if (bus_dmamem_map(sc->sc_dmat, &segs, 1,
- sizeof(struct gtidmac_desc) * GTIDMAC_NDESC * idmac_nchan,
- (void **)&sc->sc_dbuf, BUS_DMA_NOWAIT)) {
- aprint_error_dev(self,
- "bus_dmamem_map failed: descriptor buffer\n");
- goto fail5;
- }
- if (bus_dmamap_create(sc->sc_dmat,
- sizeof(struct gtidmac_desc) * GTIDMAC_NDESC * idmac_nchan, 1,
- sizeof(struct gtidmac_desc) * GTIDMAC_NDESC * idmac_nchan, 0,
- BUS_DMA_NOWAIT, &sc->sc_dmap)) {
- aprint_error_dev(self,
- "bus_dmamap_create failed: descriptor buffer\n");
- goto fail6;
- }
- if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmap, sc->sc_dbuf,
- sizeof(struct gtidmac_desc) * GTIDMAC_NDESC * idmac_nchan, NULL,
- BUS_DMA_NOWAIT)) {
- aprint_error_dev(self,
- "bus_dmamap_load failed: descriptor buffer\n");
- goto fail7;
- }
- SLIST_INIT(&sc->sc_dlist);
- for (i = 0; i < GTIDMAC_NDESC * idmac_nchan; i++) {
- dd = &sc->sc_dd_buffer[i];
- dd->dd_index = i;
- dd->dd_idmac_vaddr = &sc->sc_dbuf[i];
- dd->dd_paddr = sc->sc_dmap->dm_segs[0].ds_addr +
- (sizeof(struct gtidmac_desc) * i);
- SLIST_INSERT_HEAD(&sc->sc_dlist, dd, dd_next);
- }
-
- /* Initialize IDMAC DMA channels */
- mask = 0;
- for (i = 0; i < idmac_nchan; i++) {
- if (i > 0 &&
- ((i * GTIDMAC_I_BITS) & 31 /*bit*/) == 0) {
- bus_space_write_4(sc->sc_iot, sc->sc_ioh,
- GTIDMAC_IMR(i - 1), mask);
- mask = 0;
- }
-
- if (bus_dmamap_create(sc->sc_dmat, GTIDMAC_MAXXFER,
- GTIDMAC_NSEGS, GTIDMAC_MAXXFER, 0, BUS_DMA_NOWAIT,
- &sc->sc_cdesc[i].chan_in)) {
- aprint_error_dev(self,
- "bus_dmamap_create failed: chan%d in\n", i);
- goto fail8;
- }
- if (bus_dmamap_create(sc->sc_dmat, GTIDMAC_MAXXFER,
- GTIDMAC_NSEGS, GTIDMAC_MAXXFER, 0, BUS_DMA_NOWAIT,
- &sc->sc_cdesc[i].chan_out)) {
- aprint_error_dev(self,
- "bus_dmamap_create failed: chan%d out\n", i);
- bus_dmamap_destroy(sc->sc_dmat,
- sc->sc_cdesc[i].chan_in);
- goto fail8;
- }
- sc->sc_cdesc[i].chan_totalcnt = 0;
- sc->sc_cdesc[i].chan_running = NULL;
-
- /* Ignore bits overflow. The mask is 32bit. */
- mask |= GTIDMAC_I(i,
- GTIDMAC_I_COMP |
- GTIDMAC_I_ADDRMISS |
- GTIDMAC_I_ACCPROT |
- GTIDMAC_I_WRPROT |
- GTIDMAC_I_OWN);
- }
- if (i > 0)
- bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTIDMAC_IMR(i - 1),
- mask);
-
- /* Setup interrupt */
- for (j = 0; j < GTIDMAC_NINTRRUPT; j++) {
- int c = j * idmac_nchan / __arraycount(sc->sc_intrarg);
-
- sc->sc_intrarg[j].ia_sc = sc;
- sc->sc_intrarg[j].ia_cause = GTIDMAC_ICR(c);
- sc->sc_intrarg[j].ia_eaddr = GTIDMAC_EAR(c);
- sc->sc_intrarg[j].ia_eselect = GTIDMAC_ESR(c);
- marvell_intr_establish(mva->mva_irq + j, IPL_BIO,
- gtidmac_intr, &sc->sc_intrarg[j]);
+ if (!prop_dictionary_get_uint32(dict, "dmb_speed", &dmb_speed)) {
+ aprint_error_dev(self, "no dmb_speed property\n");
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