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[src/trunk]: src/sys/dev Add two workarounds for ICH8 with igp3.
details: https://anonhg.NetBSD.org/src/rev/395621f944fc
branches: trunk
changeset: 752793:395621f944fc
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Sun Mar 07 07:53:37 2010 +0000
description:
Add two workarounds for ICH8 with igp3.
- Workaround for 82566 Kumeran PCS lock loss.
- WOL from S5 stops working.
diffstat:
sys/dev/mii/igphy.c | 12 +-----
sys/dev/mii/igphyvar.h | 39 ++++++++++++++++++++++
sys/dev/pci/if_wm.c | 88 ++++++++++++++++++++++++++++++++++++++++++++++++-
sys/dev/pci/if_wmreg.h | 10 +++++-
4 files changed, 136 insertions(+), 13 deletions(-)
diffs (249 lines):
diff -r e3f631f764b5 -r 395621f944fc sys/dev/mii/igphy.c
--- a/sys/dev/mii/igphy.c Sun Mar 07 07:33:29 2010 +0000
+++ b/sys/dev/mii/igphy.c Sun Mar 07 07:53:37 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: igphy.c,v 1.20 2009/12/16 14:37:26 msaitoh Exp $ */
+/* $NetBSD: igphy.c,v 1.21 2010/03/07 07:53:37 msaitoh Exp $ */
/*
* The Intel copyright applies to the analog register setup, and the
@@ -70,7 +70,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: igphy.c,v 1.20 2009/12/16 14:37:26 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: igphy.c,v 1.21 2010/03/07 07:53:37 msaitoh Exp $");
#include "opt_mii.h"
@@ -88,15 +88,9 @@
#include <dev/mii/miivar.h>
#include <dev/mii/miidevs.h>
#include <dev/mii/igphyreg.h>
+#include <dev/mii/igphyvar.h>
#include <dev/pci/if_wmvar.h>
-struct igphy_softc {
- struct mii_softc sc_mii;
- int sc_smartspeed;
- uint32_t sc_mactype;
- uint32_t sc_macflags;
-};
-
static void igphy_reset(struct mii_softc *);
static void igphy_load_dspcode(struct mii_softc *);
static void igphy_load_dspcode_igp3(struct mii_softc *);
diff -r e3f631f764b5 -r 395621f944fc sys/dev/mii/igphyvar.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/dev/mii/igphyvar.h Sun Mar 07 07:53:37 2010 +0000
@@ -0,0 +1,39 @@
+/* $NetBSD: igphyvar.h,v 1.1 2010/03/07 07:53:37 msaitoh Exp $ */
+
+/*-
+ * Copyright (c) 2010 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEV_MII_IGPHYVAR_H_
+#define _DEV_MII_IGPHYVAR_H_
+
+struct igphy_softc {
+ struct mii_softc sc_mii;
+ int sc_smartspeed;
+ uint32_t sc_mactype;
+ uint32_t sc_macflags;
+};
+
+#endif /* _DEV_MII_IGPHYVAR_H_ */
diff -r e3f631f764b5 -r 395621f944fc sys/dev/pci/if_wm.c
--- a/sys/dev/pci/if_wm.c Sun Mar 07 07:33:29 2010 +0000
+++ b/sys/dev/pci/if_wm.c Sun Mar 07 07:53:37 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.201 2010/03/07 07:09:00 msaitoh Exp $ */
+/* $NetBSD: if_wm.c,v 1.202 2010/03/07 07:53:37 msaitoh Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -76,7 +76,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.201 2010/03/07 07:09:00 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.202 2010/03/07 07:53:37 msaitoh Exp $");
#include "rnd.h"
@@ -118,9 +118,11 @@
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
+#include <dev/mii/miidevs.h>
#include <dev/mii/mii_bitbang.h>
#include <dev/mii/ikphyreg.h>
#include <dev/mii/igphyreg.h>
+#include <dev/mii/igphyvar.h>
#include <dev/mii/inbmphyreg.h>
#include <dev/pci/pcireg.h>
@@ -576,6 +578,8 @@
static int wm_check_reset_block(struct wm_softc *);
static void wm_get_hw_control(struct wm_softc *);
static int wm_check_for_link(struct wm_softc *);
+static void wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *);
+static void wm_gig_downshift_workaround_ich8lan(struct wm_softc *);
static void wm_hv_phy_workaround_ich8lan(struct wm_softc *);
static void wm_k1_gig_workaround_hv(struct wm_softc *, int);
static void wm_configure_k1_ich8lan(struct wm_softc *, int);
@@ -3179,6 +3183,9 @@
sc->sc_ctrl |= CTRL_FD;
CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
}
+ } else if ((sc->sc_type == WM_T_ICH8)
+ && (sc->sc_phytype == WMPHY_IGP_3)) {
+ wm_kmrn_lock_loss_workaround_ich8lan(sc);
} else if (sc->sc_type == WM_T_PCH) {
wm_k1_gig_workaround_hv(sc,
((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0));
@@ -5433,7 +5440,20 @@
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
sc->sc_phytype = WMPHY_NONE;
} else {
- ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
+ /* Check PHY type */
+ uint32_t model;
+ struct mii_softc *child;
+
+ child = LIST_FIRST(&sc->sc_mii.mii_phys);
+ if (device_is_a(child->mii_dev, "igphy")) {
+ struct igphy_softc *isc = (struct igphy_softc *)child;
+
+ model = isc->sc_mii.mii_mpd_model;
+ if (model == MII_MODEL_yyINTEL_I82566)
+ sc->sc_phytype = WMPHY_IGP_3;
+ }
+
+ ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO);
}
}
@@ -6848,6 +6868,68 @@
return 0;
}
+/* Work-around for 82566 Kumeran PCS lock loss */
+static void
+wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *sc)
+{
+ int miistatus, active, i;
+ int reg;
+
+ miistatus = sc->sc_mii.mii_media_status;
+
+ /* If the link is not up, do nothing */
+ if ((miistatus & IFM_ACTIVE) != 0)
+ return;
+
+ active = sc->sc_mii.mii_media_active;
+
+ /* Nothing to do if the link is other than 1Gbps */
+ if (IFM_SUBTYPE(active) != IFM_1000_T)
+ return;
+
+ for (i = 0; i < 10; i++) {
+ /* read twice */
+ reg = wm_gmii_i80003_readreg(sc->sc_dev, 1, IGP3_KMRN_DIAG);
+ reg = wm_gmii_i80003_readreg(sc->sc_dev, 1, IGP3_KMRN_DIAG);
+ if ((reg & IGP3_KMRN_DIAG_PCS_LOCK_LOSS) != 0)
+ goto out; /* GOOD! */
+
+ /* Reset the PHY */
+ wm_gmii_reset(sc);
+ delay(5*1000);
+ }
+
+ /* Disable GigE link negotiation */
+ reg = CSR_READ(sc, WMREG_PHY_CTRL);
+ reg |= PHY_CTRL_GBE_DIS | PHY_CTRL_NOND0A_GBE_DIS;
+ CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
+
+ /*
+ * Call gig speed drop workaround on Gig disable before accessing
+ * any PHY registers.
+ */
+ wm_gig_downshift_workaround_ich8lan(sc);
+
+out:
+ return;
+}
+
+/* WOL from S5 stops working */
+static void
+wm_gig_downshift_workaround_ich8lan(struct wm_softc *sc)
+{
+ uint16_t kmrn_reg;
+
+ /* Only for igp3 */
+ if (sc->sc_phytype == WMPHY_IGP_3) {
+ kmrn_reg = wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_DIAG);
+ kmrn_reg |= KUMCTRLSTA_DIAG_NELPBK;
+ wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_DIAG, kmrn_reg);
+ kmrn_reg &= ~KUMCTRLSTA_DIAG_NELPBK;
+ wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_DIAG, kmrn_reg);
+ }
+}
+
/*
* Workaround for pch's PHYs
* XXX should be moved to new PHY driver?
diff -r e3f631f764b5 -r 395621f944fc sys/dev/pci/if_wmreg.h
--- a/sys/dev/pci/if_wmreg.h Sun Mar 07 07:33:29 2010 +0000
+++ b/sys/dev/pci/if_wmreg.h Sun Mar 07 07:53:37 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wmreg.h,v 1.38 2010/02/16 15:17:17 msaitoh Exp $ */
+/* $NetBSD: if_wmreg.h,v 1.39 2010/03/07 07:53:37 msaitoh Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -757,6 +757,9 @@
#define KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT 0x00000500
#define KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
+/* Diag */
+#define KUMCTRLSTA_DIAG_NELPBK 0x1000
+
/* K1 Config */
#define KUMCTRLSTA_K1_ENABLE 0x0002
@@ -833,6 +836,11 @@
#define E1000_EXTCNF_CTRL_SWFLAG EXTCNFCTR_MDIO_SW_OWNERSHIP
#define WMREG_PHY_CTRL 0x0f10 /* PHY control */
+#define PHY_CTRL_SPD_EN (1 << 0)
+#define PHY_CTRL_D0A_LPLU (1 << 1)
+#define PHY_CTRL_NOND0A_LPLU (1 << 2)
+#define PHY_CTRL_NOND0A_GBE_DIS (1 << 3)
+#define PHY_CTRL_GBE_DIS (1 << 4)
/* ich8 flash control */
#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */
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