[src/trunk]: src/sys/arch Use CR_ control regsiter definition for consistency.

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/add787645e85
branches:  trunk
changeset: 778577:add787645e85
user:      skrll <skrll%NetBSD.org@localhost>
date:      Thu Apr 05 19:42:13 2012 +0000

description:
Use CR_ control regsiter definition for consistency.

diffstat:

 sys/arch/hp700/hp700/locore.S |  13 +++++--------
 sys/arch/hppa/hppa/trap.S     |  18 +++++++++---------
 2 files changed, 14 insertions(+), 17 deletions(-)

diffs (124 lines):

diff -r 73ad92696b57 -r add787645e85 sys/arch/hp700/hp700/locore.S
--- a/sys/arch/hp700/hp700/locore.S     Thu Apr 05 16:31:53 2012 +0000
+++ b/sys/arch/hp700/hp700/locore.S     Thu Apr 05 19:42:13 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.58 2012/01/03 06:11:21 skrll Exp $        */
+/*     $NetBSD: locore.S,v 1.59 2012/04/05 19:42:13 skrll Exp $        */
 /*     $OpenBSD: locore.S,v 1.158 2008/07/28 19:08:46 miod Exp $       */
 
 /*
@@ -79,9 +79,6 @@
 /* Some aliases for the macros in assym.h. */
 #define        TRAPFRAME_SIZEOF        trapframe_SIZEOF
 
-#define        ccr     cr10
-#define        rctr    cr0
-
 /*
  * Very crude debugging macros that write to com1.
  */
@@ -244,7 +241,7 @@
        /*
         * disable all coprocessors
         */
-       mtctl   %r0, %ccr
+       mtctl   %r0, CR_CCR
 
 #ifdef MULTIPROCESSOR
 
@@ -446,7 +443,7 @@
        /*
         * disable all coprocessors
         */
-       mtctl   %r0, %ccr
+       mtctl   %r0, CR_CCR
 
        /*
         * to keep the spl() routines consistent we need to put the correct
@@ -1054,13 +1051,13 @@
         * states.
         */
        GET_CURCPU(%t1)
-       mfctl   %ccr, %r1
+       mfctl   CR_CCR, %r1
        mfctl   CR_FPPADDR, %t2
        ldw     CI_FPU_STATE(%t1), %t1
        depi    0, 25, 2, %r1           ; disables the FPU
        comb,<>,n %t1, %t2, 0           ; nullify if LWPs different
        depi    3, 25, 2, %r1           ; enables the FPU
-       mtctl   %r1, %ccr
+       mtctl   %r1, CR_CCR
 
 switch_return:
        copy    %arg0, %ret0
diff -r 73ad92696b57 -r add787645e85 sys/arch/hppa/hppa/trap.S
--- a/sys/arch/hppa/hppa/trap.S Thu Apr 05 16:31:53 2012 +0000
+++ b/sys/arch/hppa/hppa/trap.S Thu Apr 05 19:42:13 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: trap.S,v 1.63 2012/02/26 08:28:57 skrll Exp $  */
+/*     $NetBSD: trap.S,v 1.64 2012/04/05 19:42:14 skrll Exp $  */
 
 /*-
  * Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -513,7 +513,7 @@
        mtctl   %t2, CR_FPPADDR
 
        ldw     TF_CR0(%sr3, %t3), %t1
-       mtctl   %t1, %rctr
+       mtctl   %t1, CR_RCTR
 
        GET_CURCPU_SPACE(%sr3, %t3)
 
@@ -939,7 +939,7 @@
         * We have a hardware FPU.  If it is enabled,  branch to emulate the
         * instruction.
         */
-       mfctl   %ccr, %arg0
+       mfctl   CR_CCR, %arg0
        extru,= %arg0, 25, 2, %r1
        b,n     L$emulate_fpu
 
@@ -1055,10 +1055,10 @@
         * 
         * Also, branch if there's no FPU state to swap out.
         */
-       mfctl   %ccr, %r1
+       mfctl   CR_CCR, %r1
        depi    3, 25, 2, %r1
        comb,=  %r0, %arg0, L$fpu_swap_in
-       mtctl   %r1, %ccr
+       mtctl   %r1,CR_CCR 
 
        /*
         * Swap out the current FPU state.
@@ -1186,10 +1186,10 @@
 L$fpu_no_swap_in:
 
        /* We didn't swap any FPU state in, so disable the FPU. */
-       mfctl   %ccr, %r1
+       mfctl   CR_CCR, %r1
        depi    0, 25, 2, %r1
        b       L$fpu_swap_done
-       mtctl   %r1, %ccr
+       mtctl   %r1, CR_CCR 
 EXIT(hppa_fpu_swapout)
 
        /* Construct the virtual address tag. */
@@ -2053,7 +2053,7 @@
        stw     %r1, CI_TRAPSAVE + TF_FLAGS(%t3)
 
        /* gotta get it before R is up */
-       mfctl   %rctr, %t1
+       mfctl   CR_RCTR, %t1
 
        copy    %sp, %t3
        ldo     HPPA_FRAME_SIZE+TRAPFRAME_SIZEOF(%sp), %sp
@@ -2073,7 +2073,7 @@
         * %sp is loaded w/ the right VA (we did not need it being physical)
         */
 
-       mfctl   %ccr, %t2
+       mfctl   CR_CCR, %t2
        stw     %t1, TF_CR0(%sr3, %t3)
        stw     %t2, TF_CR10(%sr3, %t3)