[src/trunk]: src/sys/dev/pci Add some PCI Express definitions, MSI, MSIX, etc.

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/9495360b2f8e
branches:  trunk
changeset: 759496:9495360b2f8e
user:      matt <matt%NetBSD.org@localhost>
date:      Sat Dec 11 18:17:39 2010 +0000

description:
Add some PCI Express definitions, MSI, MSIX, etc.

diffstat:

 sys/dev/pci/pcireg.h |  55 ++++++++++++++++++++++++++++++++++++++++++++++++---
 1 files changed, 51 insertions(+), 4 deletions(-)

diffs (83 lines):

diff -r a5321d76cab6 -r 9495360b2f8e sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h      Sat Dec 11 18:12:45 2010 +0000
+++ b/sys/dev/pci/pcireg.h      Sat Dec 11 18:17:39 2010 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pcireg.h,v 1.67 2010/03/20 00:23:41 dyoung Exp $       */
+/*     $NetBSD: pcireg.h,v 1.68 2010/12/11 18:17:39 matt Exp $ */
 
 /*
  * Copyright (c) 1995, 1996, 1999, 2000
@@ -94,6 +94,7 @@
 #define        PCI_COMMAND_BACKTOBACK_ENABLE           0x00000200
 #define        PCI_COMMAND_INTERRUPT_DISABLE           0x00000400
 
+#define        PCI_STATUS_INT_STATUS                   0x00080000
 #define        PCI_STATUS_CAPLIST_SUPPORT              0x00100000
 #define        PCI_STATUS_66MHZ_SUPPORT                0x00200000
 #define        PCI_STATUS_UDF_SUPPORT                  0x00400000
@@ -345,9 +346,12 @@
 /*
  * PCI header type
  */
-#define PCI_HDRTYPE_DEVICE     0
-#define PCI_HDRTYPE_PPB                1
-#define PCI_HDRTYPE_PCB                2
+#define PCI_HDRTYPE_DEVICE     0       /* PCI/PCIX/Cardbus */
+#define PCI_HDRTYPE_PPB                1       /* PCI/PCIX/Cardbus */
+#define PCI_HDRTYPE_PCB                2       /* PCI/PCIX/Cardbus */
+#define PCI_HDRTYPE_EP         0       /* PCI Express */
+#define PCI_HDRTYPE_RC         1       /* PCI Express */
+
 
 /*
  * Mapping registers
@@ -464,6 +468,49 @@
 #define        PCI_VPD_DATAREG(ofs)    ((ofs) + 4)
 #define        PCI_VPD_OPFLAG          0x80000000
 
+#define        PCI_MSI_CTL_PERVEC_MASK 0x01000000
+#define        PCI_MSI_CTL_64BIT_ADDR  0x00800000
+#define        PCI_MSI_CTL_MME_MASK    0x7
+#define        PCI_MSI_CTL_MME_SHIFT   20
+#define        PCI_MSI_CTL_MME(ofs)    (((ofs) & PCI_MSI_CTL_MME_MASK) << PCI_MSI_CTL_MME_SHIFT)
+#define        PCI_MSI_CTL_MMC_MASK    0x7
+#define        PCI_MSI_CTL_MMC_SHIFT   17
+#define        PCI_MSI_CTL_MMC(ofs)    (((ofs) >> PCI_MSI_CTL_MME_SHIFT) & PCI_MSI_CTL_MME_MASK)
+#define        PCI_MSI_CTL_MSI_ENABLE  0x00010000
+/*
+ * MSI Message Address is at offset 4.
+ * MSI Message Upper Address (if 64bit) is at offset 8.
+ * MSI Message data is at offset 8 or 12 and is 16 bits.
+ * [16 bit reserved field]
+ * MSI Mask Bits (32 bit field)
+ * MSI Pending Bits (32 bit field)
+ */
+
+#define        PCI_MSIX_CTL_ENABLE     0x80000000
+#define        PCI_MSIX_CTL_FUNCMASK   0x40000000
+#define        PCI_MSIX_CTL_TBLSIZE_MASK 0x07ff0000
+#define        PCI_MSIX_CTL_TBLSIZE_SHIFT 16
+#define        PCI_MSIX_CTL_TBLSIZE(ofs)       (((ofs) >> PCI_MSIX_CTL_TBLSIZE_SHIFT) & PCI_MSIX_CTL_TBLSIZE_MASK)
+/*
+ * 2nd DWORD is the Table Offset
+ */
+#define        PCI_MSIX_TBLOFFSET_MASK 0xfffffff8
+#define        PCI_MSIX_TBLBIR_MASK    0x00000007
+/*
+ * 3rd DWORD is the Pending Bitmap Array Offset
+ */
+#define        PCI_MSIX_PBAOFFSET_MASK 0xfffffff8
+#define        PCI_MSIX_PBABIR_MASK    0x00000007
+
+struct pci_msix_table_entry {
+       uint32_t pci_msix_addr_lo;
+       uint32_t pci_msix_addr_hi;
+       uint32_t pci_msix_value;
+       uint32_t pci_msix_vendor_control;
+};
+#define        PCI_MSIX_VENDCTL_MASK   0x00000001
+
+
 /*
  * Power Management Capability; access via capability pointer.
  */