[src/trunk]: src/sys/arch/bebox Add experimental support GENERIC.MP.

[kiyohara <kiyohara%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/7d650b8ef247
branches:  trunk
changeset: 782207:7d650b8ef247
user:      kiyohara <kiyohara%NetBSD.org@localhost>
date:      Sat Oct 20 14:53:37 2012 +0000

description:
Add experimental support GENERIC.MP.

diffstat:

 sys/arch/bebox/bebox/cpu.c       |  140 +++++++++++++++++++++++++++++++++++---
 sys/arch/bebox/bebox/ipi_bebox.c |   86 +++++++++++++++++++++++
 sys/arch/bebox/bebox/locore.S    |   19 +++++-
 sys/arch/bebox/bebox/pic_bebox.c |   11 ++-
 sys/arch/bebox/conf/GENERIC.MP   |    7 +
 sys/arch/bebox/conf/files.bebox  |    4 +-
 sys/arch/bebox/include/cpu.h     |   20 +++++-
 sys/arch/bebox/include/intr.h    |    4 +-
 8 files changed, 274 insertions(+), 17 deletions(-)

diffs (truncated from 419 to 300 lines):

diff -r 51459b8d53bb -r 7d650b8ef247 sys/arch/bebox/bebox/cpu.c
--- a/sys/arch/bebox/bebox/cpu.c        Sat Oct 20 14:42:20 2012 +0000
+++ b/sys/arch/bebox/bebox/cpu.c        Sat Oct 20 14:53:37 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpu.c,v 1.11 2011/07/01 20:34:52 dyoung Exp $  */
+/*     $NetBSD: cpu.c,v 1.12 2012/10/20 14:53:37 kiyohara Exp $        */
 
 /*-
  * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
@@ -30,21 +30,29 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.11 2011/07/01 20:34:52 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.12 2012/10/20 14:53:37 kiyohara Exp $");
+
+#include "opt_multiprocessor.h"
 
 #include <sys/param.h>
+#include <sys/bus.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 
 #include <machine/autoconf.h>
-#include <sys/bus.h>
 #include <machine/cpu.h>
 
+#include <powerpc/oea/hid.h>
+#include <powerpc/oea/spr.h>
+#include <powerpc/spr.h>
+
+#include <uvm/uvm.h>
+
+
 int cpumatch(device_t, cfdata_t, void *);
 void cpuattach(device_t, device_t, void *);
 
-CFATTACH_DECL_NEW(cpu, 0,
-    cpumatch, cpuattach, NULL, NULL);
+CFATTACH_DECL_NEW(cpu, 0, cpumatch, cpuattach, NULL, NULL);
 
 extern struct cfdriver cpu_cd;
 
@@ -52,16 +60,126 @@
 cpumatch(device_t parent, cfdata_t cfdata, void *aux)
 {
        struct confargs *ca = aux;
-  
+
        if (strcmp(ca->ca_name, cpu_cd.cd_name) != 0)
-               return (0);
-       if (cpu_info[0].ci_dev != NULL)
-               return (0);
-       return (1);
+               return 0;
+       return 1;
 }
 
 void
 cpuattach(device_t parent, device_t self, void *aux)
 {
-       (void) cpu_attach_common(self, 0);
+       struct confargs *ca = aux;
+       struct cpu_info *ci;
+       int id = ca->ca_node;
+
+       ci = cpu_attach_common(self, id);
+       if (ci == NULL)
+               return;
+
+#ifdef MULTIPROCESSOR
+       if (id > 0)
+               cpu_spinup(self, ci);
+#endif
+}
+
+
+#ifdef MULTIPROCESSOR
+
+extern volatile u_int cpu_spinstart_ack, cpu_spinstart_cpunum;
+
+int
+md_setup_trampoline(volatile struct cpu_hatch_data *h, struct cpu_info *ci)
+{
+       int blocks, i;
+       extern void cache_flush_invalidate_all(int blocks);
+
+       /*
+        * Our CPU(603e) supports control protocol for cache only MEI
+        * (Modified/Exclusive/Invalid).  Flush dirty caches myself.
+        */
+
+       h->hatch_running = -1;
+       cpu_spinstart_ack = -1;
+
+       /* Flush-invalidate all blocks */
+       blocks = curcpu()->ci_ci.dcache_size / curcpu()->ci_ci.dcache_line_size;
+       cache_flush_invalidate_all(blocks);
+
+       cpu_spinstart_cpunum = ci->ci_cpuid;
+       __asm volatile("dcbf 0,%0"::"r"(&cpu_spinstart_cpunum):"memory");
+
+       for (i = 0; i < 100000000; i++) {
+               if (cpu_spinstart_ack != -1)
+                       break;
+               __asm volatile("dcbi 0,%0"::"r"(&cpu_spinstart_ack):"memory");
+               __asm volatile("sync; isync");
+       }
+       return 1;
 }
+
+void
+md_presync_timebase(volatile struct cpu_hatch_data *h)
+{
+       uint64_t tb;
+
+       /* Sync timebase. */
+       tb = mftb();
+       tb += 1000000;  /* 30ms @ 33MHz */
+
+       h->hatch_tbu = tb >> 32;
+       h->hatch_tbl = tb & 0xffffffff;
+
+       while (tb > mftb())
+               ;
+
+       h->hatch_running = 0;
+
+       delay(500000);
+}
+
+void
+md_start_timebase(volatile struct cpu_hatch_data *h)
+{
+       /* Nothing */
+}
+
+void
+md_sync_timebase(volatile struct cpu_hatch_data *h)
+{
+       u_int tbu, tbl;
+
+       do {
+               __asm volatile("dcbi 0,%0"::"r"(&h->hatch_running):"memory");
+               __asm volatile("sync; isync");
+
+               __asm volatile("dcbst 0,%0"::"r"(&h->hatch_running):"memory");
+               __asm volatile("sync; isync");
+       } while (h->hatch_running == -1);
+
+       __asm volatile("dcbi 0,%0"::"r"(&h->hatch_tbu):"memory");
+       __asm volatile("dcbi 0,%0"::"r"(&h->hatch_tbl):"memory");
+       __asm volatile("sync; isync");
+       __asm volatile("dcbst 0,%0"::"r"(&h->hatch_tbu):"memory");
+       __asm volatile("dcbst 0,%0"::"r"(&h->hatch_tbl):"memory");
+       __asm volatile("sync; isync");
+
+       /* Sync timebase. */
+       tbu = h->hatch_tbu;
+       tbl = h->hatch_tbl;
+       __asm volatile ("sync; isync");
+       __asm volatile ("mttbl %0" :: "r"(0));
+       __asm volatile ("mttbu %0" :: "r"(tbu));
+       __asm volatile ("mttbl %0" :: "r"(tbl));
+}
+
+void
+md_setup_interrupts(void)
+{
+
+       CLEAR_BEBOX_REG(CPU1_INT_MASK, BEBOX_INTR_MASK);
+
+       /* XXXXXX: We can handle interrupts on CPU0 only now. */
+}
+
+#endif /* MULTIPROCESSOR */
diff -r 51459b8d53bb -r 7d650b8ef247 sys/arch/bebox/bebox/ipi_bebox.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/bebox/bebox/ipi_bebox.c  Sat Oct 20 14:53:37 2012 +0000
@@ -0,0 +1,86 @@
+/* $NetBSD: ipi_bebox.c,v 1.1 2012/10/20 14:53:37 kiyohara Exp $ */
+
+/*-
+ * Copyright (c) 2007 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Tim Rightnour
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: ipi_bebox.c,v 1.1 2012/10/20 14:53:37 kiyohara Exp $");
+
+#include <sys/atomic.h>
+#include <sys/cpu.h>
+
+#include <powerpc/pic/picvar.h>
+#include <powerpc/pic/ipivar.h>
+
+
+static void bebox_send_ipi(cpuid_t, uint32_t);
+static void bebox_establish_ipi(int, int, void *);
+
+void
+setup_bebox_ipi(void)
+{
+
+       ipiops.ppc_send_ipi = bebox_send_ipi;
+       ipiops.ppc_establish_ipi = bebox_establish_ipi;
+       ipiops.ppc_ipi_vector = IPI_VECTOR;
+}
+
+static void
+bebox_send_ipi(cpuid_t target, uint32_t mesg)
+{
+       struct cpu_info * const ci = curcpu();
+       int i;
+
+       switch (target) {
+       case IPI_DST_ALL:
+       case IPI_DST_NOTME:
+               for (i = 0; i < ncpu; i++) {
+                       struct cpu_info * const dst_ci = cpu_lookup(i);
+
+                       if (target == IPI_DST_ALL || dst_ci != ci) {
+                               atomic_or_32(&dst_ci->ci_pending_ipis, mesg);
+                       }
+               }
+               break;
+
+       default:
+           {
+               struct cpu_info * const dst_ci = cpu_lookup(target);
+
+               atomic_or_32(&dst_ci->ci_pending_ipis, mesg);
+               break;
+           }
+       }
+}
+
+static void
+bebox_establish_ipi(int type, int level, void *ih_args)
+{
+       /* XXXXX: nothing? */
+}
diff -r 51459b8d53bb -r 7d650b8ef247 sys/arch/bebox/bebox/locore.S
--- a/sys/arch/bebox/bebox/locore.S     Sat Oct 20 14:42:20 2012 +0000
+++ b/sys/arch/bebox/bebox/locore.S     Sat Oct 20 14:53:37 2012 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.27 2012/10/20 12:45:22 kiyohara Exp $     */
+/*     $NetBSD: locore.S,v 1.28 2012/10/20 14:53:37 kiyohara Exp $     */
 /*     $OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $       */
 
 /*
@@ -178,6 +178,23 @@
 
 loop:  b       loop                    /* XXX not reached */
 
+
+       .globl  _C_LABEL(cache_flush_invalidate_all)
+_C_LABEL(cache_flush_invalidate_all):
+       mtctr   3
+       li      4,0x0
+loop1: lwz     5,0(4)
+       addi    4,4,32
+       bdnz    loop1
+
+       mtctr   3
+       li      4,0x0
+loop2: dcbf    0,4
+       addi    4,4,32
+       bdnz    loop2
+
+       blr
+
        .globl  _C_LABEL(debug_led)
 _C_LABEL(debug_led):
        lis     4, 0x8000
diff -r 51459b8d53bb -r 7d650b8ef247 sys/arch/bebox/bebox/pic_bebox.c