[src/trunk]: src/sys/arch/arm/arm Add a few more DSBs before flushing cache l...

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/b72091798da2
branches:  trunk
changeset: 782126:b72091798da2
user:      matt <matt%NetBSD.org@localhost>
date:      Wed Oct 17 18:55:43 2012 +0000

description:
Add a few more DSBs before flushing cache lines.

diffstat:

 sys/arch/arm/arm/cpufunc_asm_armv7.S |  3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diffs (27 lines):

diff -r c80834944391 -r b72091798da2 sys/arch/arm/arm/cpufunc_asm_armv7.S
--- a/sys/arch/arm/arm/cpufunc_asm_armv7.S      Wed Oct 17 18:53:45 2012 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_armv7.S      Wed Oct 17 18:55:43 2012 +0000
@@ -139,6 +139,7 @@
        and     r3, r0, ip              @ get offset into cache line
        add     r1, r1, r3              @ add to length
        bic     r0, r0, ip              @ clear offset from start.
+       dsb
 1:
        mcr     p15, 0, r0, c7, c10, 1  @ wb the D-Cache to PoC
        add     r0, r0, r2
@@ -158,6 +159,7 @@
        and     r3, r0, ip              @ get offset into cache line
        add     r1, r1, r3              @ add to length
        bic     r0, r0, ip              @ clear offset from start.
+       dsb
 1:
        mcr     p15, 0, r0, c7, c14, 1  @ wb and inv the D-Cache line
        add     r0, r0, r2
@@ -198,6 +200,7 @@
        and     r3, r0, ip              @ get offset into cache line
        add     r1, r1, r3              @ add to length
        bic     r0, r0, ip              @ clear offset from start.
+       dsb
 1:
        mcr     p15, 0, r0, c7, c5, 1   @ invalidate the I-Cache line
        mcr     p15, 0, r0, c7, c14, 1  @ wb and inv the D-Cache line