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[src/trunk]: src/sys/arch/arm/broadcom Add code to init the SRAB (the switch ...
details: https://anonhg.NetBSD.org/src/rev/927fab6cc186
branches: trunk
changeset: 781841:927fab6cc186
user: matt <matt%NetBSD.org@localhost>
date: Wed Oct 03 19:18:40 2012 +0000
description:
Add code to init the SRAB (the switch robot). Don't configure eth3 by default.
diffstat:
sys/arch/arm/broadcom/bcm53xx_board.c | 127 +++++++++++++++++++++++++-
sys/arch/arm/broadcom/bcm53xx_ccb.c | 6 +-
sys/arch/arm/broadcom/bcm53xx_reg.h | 164 +++++++++++++++++++++++++++++----
sys/arch/arm/broadcom/bcm53xx_var.h | 7 +-
4 files changed, 276 insertions(+), 28 deletions(-)
diffs (truncated from 432 to 300 lines):
diff -r 2181f0e9b550 -r 927fab6cc186 sys/arch/arm/broadcom/bcm53xx_board.c
--- a/sys/arch/arm/broadcom/bcm53xx_board.c Wed Oct 03 19:17:00 2012 +0000
+++ b/sys/arch/arm/broadcom/bcm53xx_board.c Wed Oct 03 19:18:40 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bcm53xx_board.c,v 1.3 2012/09/18 05:47:27 matt Exp $ */
+/* $NetBSD: bcm53xx_board.c,v 1.4 2012/10/03 19:18:40 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -34,7 +34,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.3 2012/09/18 05:47:27 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.4 2012/10/03 19:18:40 matt Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -43,10 +43,14 @@
#include <prop/proplib.h>
+#include <net/if.h>
+#include <net/if_ether.h>
+
#define CRU_PRIVATE
#define DDR_PRIVATE
#define DMU_PRIVATE
#define ARMCORE_PRIVATE
+#define SRAB_PRIVATE
#include <arm/cortex/a9tmr_var.h>
#include <arm/cortex/pl310_var.h>
@@ -519,5 +523,122 @@
prop_dictionary_set_uint32(dict, "frequency",
clk_info.clk_cpu / 2);
return;
- }
+ }
+
+ if (device_is_a(self, "bcmeth")) {
+ const struct bcmccb_attach_args * const ccbaa = aux;
+ const uint8_t enaddr[ETHER_ADDR_LEN] = {
+ 0x00, 0x01, 0x02, 0x03, 0x04,
+ 0x05 + 2 * ccbaa->ccbaa_loc.loc_port,
+ };
+ prop_data_t pd = prop_data_create_data(enaddr, ETHER_ADDR_LEN);
+ KASSERT(pd != NULL);
+ if (prop_dictionary_set(device_properties(self), "mac-address", pd) == false) {
+ printf("WARNING: Unable to set mac-address property for %s\n", device_xname(self));
+ }
+ prop_object_release(pd);
+ }
+}
+
+static kmutex_t srab_lock __cacheline_aligned;
+
+void
+bcm53xx_srab_init(void)
+{
+ mutex_init(&srab_lock, MUTEX_DEFAULT, IPL_VM);
+
+ bcm53xx_srab_write_4(0x0079, 0x90); // reset switch
+ for (u_int port = 0; port < 8; port++) {
+ /* per port control: no stp */
+ bcm53xx_srab_write_4(port, 0x00);
+ }
+ bcm53xx_srab_write_4(0x0008, 0x1c); // IMP port (enab UC/MC/BC)
+ bcm53xx_srab_write_4(0x000e, 0xbb); // IMP port force-link 1G
+ bcm53xx_srab_write_4(0x005d, 0x7b); // port5 force-link 1G
+ bcm53xx_srab_write_4(0x005f, 0x7b); // port7 force-link 1G
+ bcm53xx_srab_write_4(0x000b, 0x7); // management mode
+ bcm53xx_srab_write_4(0x0203, 0x0); // disable BRCM tag
+ bcm53xx_srab_write_4(0x0200, 0x80); // enable IMP=port8
+}
+
+static inline void
+bcm53xx_srab_busywait(bus_space_tag_t bst, bus_space_handle_t bsh)
+{
+ while (bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT) & SRA_GORDYN) {
+ delay(10);
+ }
}
+
+uint32_t
+bcm53xx_srab_read_4(u_int pageoffset)
+{
+ bus_space_tag_t bst = bcm53xx_ioreg_bst;
+ bus_space_handle_t bsh = bcm53xx_ioreg_bsh;
+ uint32_t rv;
+
+ mutex_spin_enter(&srab_lock);
+
+ bcm53xx_srab_busywait(bst, bsh);
+ bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT,
+ __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN);
+ bcm53xx_srab_busywait(bst, bsh);
+ rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL);
+
+ mutex_spin_exit(&srab_lock);
+ return rv;
+}
+
+uint64_t
+bcm53xx_srab_read_8(u_int pageoffset)
+{
+ bus_space_tag_t bst = bcm53xx_ioreg_bst;
+ bus_space_handle_t bsh = bcm53xx_ioreg_bsh;
+ uint64_t rv;
+
+ mutex_spin_enter(&srab_lock);
+
+ bcm53xx_srab_busywait(bst, bsh);
+ bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT,
+ __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_GORDYN);
+ bcm53xx_srab_busywait(bst, bsh);
+ rv = bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDH);
+ rv <<= 32;
+ rv |= bus_space_read_4(bst, bsh, SRAB_BASE + SRAB_RDL);
+
+ mutex_spin_exit(&srab_lock);
+ return rv;
+}
+
+void
+bcm53xx_srab_write_4(u_int pageoffset, uint32_t val)
+{
+ bus_space_tag_t bst = bcm53xx_ioreg_bst;
+ bus_space_handle_t bsh = bcm53xx_ioreg_bsh;
+
+ mutex_spin_enter(&srab_lock);
+
+ bcm53xx_srab_busywait(bst, bsh);
+ bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val);
+ bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT,
+ __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN);
+ bcm53xx_srab_busywait(bst, bsh);
+
+ mutex_spin_exit(&srab_lock);
+}
+
+void
+bcm53xx_srab_write_8(u_int pageoffset, uint64_t val)
+{
+ bus_space_tag_t bst = bcm53xx_ioreg_bst;
+ bus_space_handle_t bsh = bcm53xx_ioreg_bsh;
+
+ mutex_spin_enter(&srab_lock);
+
+ bcm53xx_srab_busywait(bst, bsh);
+ bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDL, val);
+ bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_WDH, val >> 32);
+ bus_space_write_4(bst, bsh, SRAB_BASE + SRAB_CMDSTAT,
+ __SHIFTIN(pageoffset, SRA_PAGEOFFSET) | SRA_WRITE | SRA_GORDYN);
+ bcm53xx_srab_busywait(bst, bsh);
+ mutex_spin_exit(&srab_lock);
+}
diff -r 2181f0e9b550 -r 927fab6cc186 sys/arch/arm/broadcom/bcm53xx_ccb.c
--- a/sys/arch/arm/broadcom/bcm53xx_ccb.c Wed Oct 03 19:17:00 2012 +0000
+++ b/sys/arch/arm/broadcom/bcm53xx_ccb.c Wed Oct 03 19:18:40 2012 +0000
@@ -34,7 +34,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_ccb.c,v 1.2 2012/09/22 01:46:57 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_ccb.c,v 1.3 2012/10/03 19:18:41 matt Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -108,7 +108,7 @@
{ "bcmeth", GMAC0_BASE, 0x1000, 0, 1, { IRQ_GMAC0 }, },
{ "bcmeth", GMAC1_BASE, 0x1000, 1, 1, { IRQ_GMAC1 }, },
{ "bcmeth", GMAC2_BASE, 0x1000, 2, 1, { IRQ_GMAC2 }, },
- { "bcmeth", GMAC3_BASE, 0x1000, 3, 1, { IRQ_GMAC3 }, },
+ // { "bcmeth", GMAC3_BASE, 0x1000, 3, 1, { IRQ_GMAC3 }, },
{ "bcmpax", PCIE0_BASE, 0x1000, 0, 6, { IRQ_PCIE_INT0 }, },
{ "bcmpax", PCIE1_BASE, 0x1000, 1, 6, { IRQ_PCIE_INT1 }, },
{ "bcmpax", PCIE2_BASE, 0x1000, 2, 6, { IRQ_PCIE_INT2 }, },
@@ -159,6 +159,8 @@
aprint_naive("\n");
aprint_normal("\n");
+ bcm53xx_srab_init(); // need this for ethernet.
+
for (size_t i = 0; i < __arraycount(bcmccb_locators); i++) {
struct bcmccb_attach_args ccbaa = {
.ccbaa_ccb_bst = sc->sc_bst,
diff -r 2181f0e9b550 -r 927fab6cc186 sys/arch/arm/broadcom/bcm53xx_reg.h
--- a/sys/arch/arm/broadcom/bcm53xx_reg.h Wed Oct 03 19:17:00 2012 +0000
+++ b/sys/arch/arm/broadcom/bcm53xx_reg.h Wed Oct 03 19:18:40 2012 +0000
@@ -213,6 +213,20 @@
#define TIMER_FREQ BCM53XX_REF_CLK
+#ifdef SRAB_PRIVATE
+#define SRAB_CMDSTAT 0x002c
+#define SRA_PAGE __BITS(31,24)
+#define SRA_OFFSET __BITS(23,16)
+#define SRA_PAGEOFFSET __BITS(31,16)
+#define SRA_RST __BIT(2)
+#define SRA_WRITE __BIT(1)
+#define SRA_GORDYN __BIT(0)
+#define SRAB_WDH 0x0030
+#define SRAB_WDL 0x0034
+#define SRAB_RDH 0x0038
+#define SRAB_RDL 0x003c
+#endif
+
#ifdef MII_PRIVATE
#define MII_INTERNAL 0x0038003 /* internal phy bitmask */
#define MIIMGT 0x000
@@ -313,17 +327,17 @@
#define CRU_GPIO_PULL_DOWN 0x11e0
#define CRU_STRAPS_CONTROL 0x12a0
-#define STRAP_BOOT_DEV __BITS(17,16)
-#define STRAP_NAND_TYPE __BITS(15,12)
-#define STRAP_NAND_PAGE __BITS(11,10)
-#define STRAP_DDR3 __BIT(9)
-#define STRAP_P5_VOLT_15 __BIT(8)
-#define STRAP_P5_MODE __BITS(7,6)
-#define STRAP_PCIE0_MODE __BIT(5)
-#define STRAP_USB3_SEL __BIT(4)
-#define STRAP_EX_EXTCLK __BIT(3)
-#define STRAP_HW_FWDG_EN __BIT(2)
-#define STRAP_LED_SERIAL_MODE __BIT(1)
+#define STRAP_BOOT_DEV __BITS(17,16)
+#define STRAP_NAND_TYPE __BITS(15,12)
+#define STRAP_NAND_PAGE __BITS(11,10)
+#define STRAP_DDR3 __BIT(9)
+#define STRAP_P5_VOLT_15 __BIT(8)
+#define STRAP_P5_MODE __BITS(7,6)
+#define STRAP_PCIE0_MODE __BIT(5)
+#define STRAP_USB3_SEL __BIT(4)
+#define STRAP_EX_EXTCLK __BIT(3)
+#define STRAP_HW_FWDG_EN __BIT(2)
+#define STRAP_LED_SERIAL_MODE __BIT(1)
#define STRAP_BISR_BYPASS_AUTOLOAD __BIT(0)
#endif /* CRU_PRIVATE */
@@ -634,8 +648,7 @@
struct gmac_txdb {
uint32_t txdb_flags;
- uint16_t txdb_buflen;
- uint16_t txdb_addrext;
+ uint32_t txdb_buflen;
uint32_t txdb_addrlo;
uint32_t txdb_addrhi;
};
@@ -646,8 +659,7 @@
struct gmac_rxdb {
uint32_t rxdb_flags;
- uint16_t rxdb_buflen;
- uint16_t rxdb_addrext;
+ uint32_t rxdb_buflen;
uint32_t rxdb_addrlo;
uint32_t rxdb_addrhi;
};
@@ -670,10 +682,46 @@
#define RXSTS_DESC_COUNT __BITS(27,24) // # of descriptors - 1
#define GMAC_DEVCONTROL 0x000
+#define ENABLE_DEL_G_TXC __BIT(21)
+#define ENABLE_DEL_G_RXC __BIT(20)
+#define TXC_DRNG __BITS(19,18)
+#define RXC_DRNG __BITS(17,16)
+#define TXQ_FLUSH __BIT(8)
+#define NWAY_AUTO_POLL_EN __BIT(7)
+#define FLOW_CTRL_MODE __BITS(6,5)
+#define MIB_RD_RESET_EN __BIT(4)
+#define RGMII_LINK_STATUS_SEL __BIT(3)
+#define CPU_FLOW_CTRL_ON __BIT(2)
+#define RXQ_OVERFLOW_CTRL_SEL __BIT(1)
+#define TXARB_STRICT_MODE __BIT(0)
#define GMAC_DEVSTATUS 0x004
#define GMAC_BISTSTATUS 0x00c
#define GMAC_INTSTATUS 0x020
#define GMAC_INTMASK 0x024
+#define TXQECCUNCORRECTED __BIT(31)
+#define TXQECCCORRECTED __BIT(30)
+#define RXQECCUNCORRECTED __BIT(29)
+#define RXQECCCORRECTED __BIT(28)
+#define XMTINT_3 __BIT(27)
+#define XMTINT_2 __BIT(26)
+#define XMTINT_1 __BIT(25)
+#define XMTINT_0 __BIT(24)
+#define RCVINT __BIT(16)
+#define XMTUF __BIT(15)
+#define RCVFIFOOF __BIT(14)
+#define RCVDESCUF __BIT(13)
+#define DESCPROTOERR __BIT(12)
+#define DATAERR __BIT(11)
+#define DESCERR __BIT(10)
+#define INT_SW_LINK_ST_CHG __BIT(8)
+#define INT_TIMEOUT __BIT(7)
+#define MIB_TX_INT __BIT(6)
+#define MIB_RX_INT __BIT(5)
+#define MDIOINT __BIT(4)
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