[src/trunk]: src/sys/arch/arm/broadcom Add a few more PCIE registers

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/bd77b6a66750
branches:  trunk
changeset: 781673:bd77b6a66750
user:      matt <matt%NetBSD.org@localhost>
date:      Sat Sep 22 01:46:31 2012 +0000

description:
Add a few more PCIE registers

diffstat:

 sys/arch/arm/broadcom/bcm53xx_reg.h |  26 +++++++++++++++++++++++++-
 1 files changed, 25 insertions(+), 1 deletions(-)

diffs (43 lines):

diff -r fef09f3d3eed -r bd77b6a66750 sys/arch/arm/broadcom/bcm53xx_reg.h
--- a/sys/arch/arm/broadcom/bcm53xx_reg.h       Sat Sep 22 01:44:12 2012 +0000
+++ b/sys/arch/arm/broadcom/bcm53xx_reg.h       Sat Sep 22 01:46:31 2012 +0000
@@ -486,6 +486,9 @@
 
 #define        PCIE_MISC_INTR_EN       0xf1c
 #define PCIE_TX_DEBUG_CFG      0xf20
+#define        PCIE_ERROR_INTR_EN      0xf30
+#define        PCIE_ERROR_INTR_CLR     0xf34
+#define        PCIE_ERROR_INTR_STS     0xf38
 
 
 // PCIE_SYS_MSI_INTR_EN
@@ -527,7 +530,28 @@
 // PCIE_IARR_1_LOWER / UPPER
 #define        IARR1_ADDR              __BIT(31,20)
 #define        IARR1_SIZE              __BIT(7,0)
-#define        IARR0_VALID             __BIT(0)
+
+// PCIE_IARR_2_LOWER / UPPER
+#define        IARR2_ADDR              __BIT(31,20)
+#define        IARR2_SIZE              __BIT(7,0)
+
+// PCIE_MISC_INTR_EN
+#define        INTR_EN_PCIE_ERR_ATTN   __BIT(2)
+#define        INTR_EN_PAXB_ECC_2B_ATTN        __BIT(1)
+#define        INTR_EN_PCIE_IN_WAKE_B  __BIT(0)
+
+// PCIE_ERR_INTR_{EN,CLR,STS}
+#define        PCIE_OVERFLOW_UNDERFLOW_INTR    __BIT(10)
+#define        PCIE_AXI_MASTER_RRESP_SLV_ERR_INTR      __BIT(9)
+#define        PCIE_AXI_MASTER_RRESP_DECERR_INTR       __BIT(8)
+#define        PCIE_ECRC_ERR_INTR              __BIT(7)
+#define        PCIE_CMPL_TIMEROUT_INTR         __BIT(6)
+#define        PCIE_ERR_ATTN_INTR              __BIT(5)
+#define        PCIE_IN_WAKE_B_INTR             __BIT(4)
+#define        PCIE_REPLAY_BUF_2B_ECC_ERR_INTR __BIT(3)
+#define        PCIE_RD_CMPL_BUF_1_2B_ECC_ERR_INTR      __BIT(2)
+#define        PCIE_RD_CMPL_BUF_0_2B_ECC_ERR_INTR      __BIT(1)
+#define        PCIE_WR_DATA_BUF_2B_ECC_ERR_INTR        __BIT(0)
 
 #define        REGS_DEVICE_CAPACITY    0x04d4
 #define        REGS_LINK_CAPACITY      0x03dc