[src/trunk]: src/sys/arch/arm/arm Fix range ops to properly flush.

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/77295f6204bf
branches:  trunk
changeset: 781924:77295f6204bf
user:      matt <matt%NetBSD.org@localhost>
date:      Sun Oct 07 18:47:07 2012 +0000

description:
Fix range ops to properly flush.

diffstat:

 sys/arch/arm/arm/cpufunc_asm_armv7.S |  20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

diffs (58 lines):

diff -r 55fc3d207373 -r 77295f6204bf sys/arch/arm/arm/cpufunc_asm_armv7.S
--- a/sys/arch/arm/arm/cpufunc_asm_armv7.S      Sun Oct 07 18:40:49 2012 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_armv7.S      Sun Oct 07 18:47:07 2012 +0000
@@ -99,6 +99,10 @@
        and     r2, r2, #7              @ get line size (log2(size)-4, 0=16)
        mov     ip, #16                 @ make a bit mask
        lsl     r2, ip, r2              @ and shift into position
+       sub     ip, r2, #1              @ make into a mask
+       and     r3, r0, ip              @ get offset into cache line
+       add     r1, r1, r3              @ add to length
+       bic     r0, r0, ip              @ clear offset from start.
 1:
        mcr     p15, 0, r0, c7, c10, 1  @ wb the D-Cache line
        mcr     p15, 0, r0, c7, c5, 1   @ invalidate the I-Cache line
@@ -131,6 +135,10 @@
        and     r2, r2, #7              @ get line size (log2(size)-4, 0=16)
        mov     ip, #16                 @ make a bit mask
        lsl     r2, ip, r2              @ and shift into position
+       sub     ip, r2, #1              @ make into a mask
+       and     r3, r0, ip              @ get offset into cache line
+       add     r1, r1, r3              @ add to length
+       bic     r0, r0, ip              @ clear offset from start.
 1:
        mcr     p15, 0, r0, c7, c10, 1  @ wb the D-Cache to PoC
        add     r0, r0, r2
@@ -146,6 +154,10 @@
        and     r2, r2, #7              @ get line size (log2(size)-4, 0=16)
        mov     ip, #16                 @ make a bit mask
        lsl     r2, ip, r2              @ and shift into position
+       sub     ip, r2, #1              @ make into a mask
+       and     r3, r0, ip              @ get offset into cache line
+       add     r1, r1, r3              @ add to length
+       bic     r0, r0, ip              @ clear offset from start.
 1:
        mcr     p15, 0, r0, c7, c14, 1  @ wb and inv the D-Cache line
        add     r0, r0, r2
@@ -161,6 +173,10 @@
        and     r2, r2, #7              @ get line size (log2(size)-4, 0=16)
        mov     ip, #16                 @ make a bit mask
        lsl     r2, ip, r2              @ and shift into position
+       sub     ip, r2, #1              @ make into a mask
+       and     r3, r0, ip              @ get offset into cache line
+       add     r1, r1, r3              @ add to length
+       bic     r0, r0, ip              @ clear offset from start.
 1:
        mcr     p15, 0, r0, c7, c6, 1   @ invalidate the D-Cache line  
        add     r0, r0, r2 
@@ -178,6 +194,10 @@
        and     r2, r2, #7              @ get line size (log2(size)-4, 0=16)
        mov     ip, #16                 @ make a bit mask
        lsl     r2, ip, r2              @ and shift into position
+       sub     ip, r2, #1              @ make into a mask
+       and     r3, r0, ip              @ get offset into cache line
+       add     r1, r1, r3              @ add to length
+       bic     r0, r0, ip              @ clear offset from start.
 1:
        mcr     p15, 0, r0, c7, c5, 1   @ invalidate the I-Cache line
        mcr     p15, 0, r0, c7, c14, 1  @ wb and inv the D-Cache line