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[src/netbsd-6]: src/sys Pull up following revision(s) (requested by matt in t...
details: https://anonhg.NetBSD.org/src/rev/7168e66f117a
branches: netbsd-6
changeset: 774171:7168e66f117a
user: riz <riz%NetBSD.org@localhost>
date: Mon Jun 11 17:45:32 2012 +0000
description:
Pull up following revision(s) (requested by matt in ticket #254):
sys/arch/powerpc/booke/dev/pq3sdhc.c: revision 1.4
sys/dev/sdmmc/sdhc.c: revision 1.11
sys/dev/sdmmc/sdhc.c: revision 1.13
Use the new 32-bit and ESDHC support in sdhc.c
Support 32-bit only access to the SDHC registers.
Add support for FreeScale "Enhanced" SDHC port.
Add support for CGM mode (XLP and BCM2835 (Arason)).
Do not read past array end, found by gcc -O3.
This could cause to HWRITE4() a bad value, but maybe last 2 bytes are
probably ignored by hardware anyway.
diffstat:
sys/arch/powerpc/booke/dev/pq3sdhc.c | 128 +------
sys/dev/sdmmc/sdhc.c | 693 +++++++++++++++++++++++++---------
2 files changed, 513 insertions(+), 308 deletions(-)
diffs (truncated from 1258 to 300 lines):
diff -r e09ea096ce54 -r 7168e66f117a sys/arch/powerpc/booke/dev/pq3sdhc.c
--- a/sys/arch/powerpc/booke/dev/pq3sdhc.c Wed Jun 06 18:20:51 2012 +0000
+++ b/sys/arch/powerpc/booke/dev/pq3sdhc.c Mon Jun 11 17:45:32 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pq3sdhc.c,v 1.3 2011/06/29 06:12:10 matt Exp $ */
+/* $NetBSD: pq3sdhc.c,v 1.3.8.1 2012/06/11 17:45:32 riz Exp $ */
/*-
* Copyright (c) 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pq3sdhc.c,v 1.3 2011/06/29 06:12:10 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pq3sdhc.c,v 1.3.8.1 2012/06/11 17:45:32 riz Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -53,7 +53,6 @@
static void pq3sdhc_attach(device_t, device_t, void *);
struct pq3sdhc_softc {
- struct powerpc_bus_space sc_mybst;
struct sdhc_softc sc;
bus_space_tag_t sc_bst;
bus_space_handle_t sc_bsh;
@@ -64,114 +63,6 @@
CFATTACH_DECL_NEW(pq3sdhc, sizeof(struct pq3sdhc_softc),
pq3sdhc_match, pq3sdhc_attach, NULL, NULL);
-static uint8_t
-pq3sdhc_read_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
-{
- const struct pq3sdhc_softc * const sc = (const void *) t;
-
- KASSERT((o & -4) != SDHC_DATA);
-
- const uint32_t v = bus_space_read_4(sc->sc_bst, h, o & -4);
-
- return v >> ((o & 3) * 8);
-}
-
-static uint16_t
-pq3sdhc_read_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
-{
- const struct pq3sdhc_softc * const sc = (const void *) t;
-
- KASSERT((o & 1) == 0);
- KASSERT((o & -4) != SDHC_DATA);
-
- uint32_t v = bus_space_read_4(sc->sc_bst, h, o & -4);
-
- if (__predict_false(o == SDHC_HOST_VER))
- return v;
- if (__predict_false(o == SDHC_NINTR_STATUS)) {
- v |= SDHC_ERROR_INTERRUPT * ((v > 0xffff) != 0);
- if (v != 0)
- printf("get(INTR_STATUS)=%#x\n", v);
- }
- if (__predict_false(o == SDHC_EINTR_STATUS)) {
- if (v != 0)
- printf("get(INTR_STATUS)=%#x\n", v);
- }
-
- return v >> ((o & 2) * 8);
-}
-
-static uint32_t
-pq3sdhc_read_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
-{
- const struct pq3sdhc_softc * const sc = (const void *) t;
-
- KASSERT((o & 3) == 0);
-
- uint32_t v = bus_space_read_4(sc->sc_bst, h, o & -4);
-
- if (__predict_false(o == SDHC_DATA))
- v = htole32(v);
-
- return v;
-}
-
-static void
-pq3sdhc_write_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, uint8_t nv)
-{
- const struct pq3sdhc_softc * const sc = (const void *) t;
- KASSERT((o & -4) != SDHC_DATA);
- uint32_t v = bus_space_read_4(sc->sc_bst, h, o & -4);
- const u_int shift = (o & 3) * 8;
-
- if (o == SDHC_HOST_CTL) {
- nv &= ~EDSHC_HOST_CTL_RES;
- }
-
- v &= ~(0xff << shift);
- v |= (nv << shift);
-
- bus_space_write_4(sc->sc_bst, h, o & -4, v);
-}
-
-static void
-pq3sdhc_write_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, uint16_t nv)
-{
- const struct pq3sdhc_softc * const sc = (const void *) t;
- KASSERT((o & 1) == 0);
- KASSERT((o & -4) != SDHC_DATA);
- const u_int shift = (o & 2) * 8;
- uint32_t v;
-
- /*
- * Since NINTR_STATUS and EINTR_STATUS are W1C, don't bother getting
- * the previous value since we'd clear them.
- */
- if (__predict_true((o & -4) != SDHC_NINTR_STATUS)) {
- v = bus_space_read_4(sc->sc_bst, h, o & -4);
- v &= ~(0xffff << shift);
- v |= nv << shift;
- } else {
- v = nv << shift;
- printf("put(INTR_STATUS,%#x)\n", v);
- }
-
- bus_space_write_4(sc->sc_bst, h, o & -4, v);
-}
-
-static void
-pq3sdhc_write_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, uint32_t v)
-{
- const struct pq3sdhc_softc * const sc = (const void *) t;
-
- KASSERT((o & 3) == 0);
-
- if (__predict_false(o == SDHC_DATA))
- v = le32toh(v);
-
- bus_space_write_4(sc->sc_bst, h, o & -4, v);
-}
-
static int
pq3sdhc_match(device_t parent, cfdata_t cf, void *aux)
{
@@ -194,19 +85,12 @@
psc->sc_children |= cna->cna_childmask;
sc->sc.sc_dmat = cna->cna_dmat;
sc->sc.sc_dev = self;
- //sc->sc.sc_flags |= SDHC_FLAG_USE_DMA;
- sc->sc.sc_flags |= SDHC_FLAG_HAVE_DVS;
+ sc->sc.sc_flags |= SDHC_FLAG_USE_DMA;
+ sc->sc.sc_flags |=
+ SDHC_FLAG_HAVE_DVS | SDHC_FLAG_32BIT_ACCESS | SDHC_FLAG_ENHANCED;
sc->sc.sc_host = sc->sc_hosts;
sc->sc.sc_clkbase = board_info_get_number("bus-frequency") / 2000;
sc->sc_bst = cna->cna_memt;
- sc->sc_mybst = *cna->cna_memt;
-
- sc->sc_mybst.pbs_scalar.pbss_read_1 = pq3sdhc_read_1;
- sc->sc_mybst.pbs_scalar.pbss_read_2 = pq3sdhc_read_2;
- sc->sc_mybst.pbs_scalar.pbss_read_4 = pq3sdhc_read_4;
- sc->sc_mybst.pbs_scalar.pbss_write_1 = pq3sdhc_write_1;
- sc->sc_mybst.pbs_scalar.pbss_write_2 = pq3sdhc_write_2;
- sc->sc_mybst.pbs_scalar.pbss_write_4 = pq3sdhc_write_4;
error = bus_space_map(sc->sc_bst, cnl->cnl_addr, cnl->cnl_size, 0,
&sc->sc_bsh);
@@ -229,7 +113,7 @@
aprint_normal_dev(self, "interrupting on irq %d\n",
cnl->cnl_intrs[0]);
- error = sdhc_host_found(&sc->sc, &sc->sc_mybst, sc->sc_bsh,
+ error = sdhc_host_found(&sc->sc, sc->sc_bst, sc->sc_bsh,
cnl->cnl_size);
if (error != 0) {
aprint_error_dev(self, "couldn't initialize host, error=%d\n",
diff -r e09ea096ce54 -r 7168e66f117a sys/dev/sdmmc/sdhc.c
--- a/sys/dev/sdmmc/sdhc.c Wed Jun 06 18:20:51 2012 +0000
+++ b/sys/dev/sdmmc/sdhc.c Mon Jun 11 17:45:32 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sdhc.c,v 1.10 2012/02/02 22:49:17 nonaka Exp $ */
+/* $NetBSD: sdhc.c,v 1.10.2.1 2012/06/11 17:45:32 riz Exp $ */
/* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */
/*
@@ -23,7 +23,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.10 2012/02/02 22:49:17 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.10.2.1 2012/06/11 17:45:32 riz Exp $");
#ifdef _KERNEL_OPT
#include "opt_sdmmc.h"
@@ -82,30 +82,80 @@
uint32_t flags; /* flags for this host */
#define SHF_USE_DMA 0x0001
#define SHF_USE_4BIT_MODE 0x0002
+#define SHF_USE_8BIT_MODE 0x0004
};
#define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev))
-#define HREAD1(hp, reg) \
- (bus_space_read_1((hp)->iot, (hp)->ioh, (reg)))
-#define HREAD2(hp, reg) \
- (bus_space_read_2((hp)->iot, (hp)->ioh, (reg)))
-#define HREAD4(hp, reg) \
+static uint8_t
+hread1(struct sdhc_host *hp, bus_size_t reg)
+{
+ if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS))
+ return bus_space_read_1(hp->iot, hp->ioh, reg);
+
+ return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 3));
+}
+
+static uint16_t
+hread2(struct sdhc_host *hp, bus_size_t reg)
+{
+ if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS))
+ return bus_space_read_2(hp->iot, hp->ioh, reg);
+
+ return bus_space_read_4(hp->iot, hp->ioh, reg & -4) >> (8 * (reg & 2));
+}
+
+#define HREAD1(hp, reg) hread1(hp, reg)
+#define HREAD2(hp, reg) hread2(hp, reg)
+#define HREAD4(hp, reg) \
(bus_space_read_4((hp)->iot, (hp)->ioh, (reg)))
-#define HWRITE1(hp, reg, val) \
- bus_space_write_1((hp)->iot, (hp)->ioh, (reg), (val))
-#define HWRITE2(hp, reg, val) \
- bus_space_write_2((hp)->iot, (hp)->ioh, (reg), (val))
+
+
+static void
+hwrite1(struct sdhc_host *hp, bus_size_t o, uint8_t val)
+{
+ if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
+ bus_space_write_1(hp->iot, hp->ioh, o, val);
+ } else {
+ const size_t shift = 8 * (o & 3);
+ o &= -4;
+ uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o);
+ tmp = (val << shift) | (tmp & ~(0xff << shift));
+ bus_space_write_4(hp->iot, hp->ioh, o, tmp);
+ }
+}
+
+static void
+hwrite2(struct sdhc_host *hp, bus_size_t o, uint16_t val)
+{
+ if (!ISSET(hp->sc->sc_flags, SDHC_FLAG_32BIT_ACCESS)) {
+ bus_space_write_2(hp->iot, hp->ioh, o, val);
+ } else {
+ const size_t shift = 8 * (o & 2);
+ o &= -4;
+ uint32_t tmp = bus_space_read_4(hp->iot, hp->ioh, o);
+ tmp = (val << shift) | (tmp & ~(0xffff << shift));
+ bus_space_write_4(hp->iot, hp->ioh, o, tmp);
+ }
+}
+
+#define HWRITE1(hp, reg, val) hwrite1(hp, reg, val)
+#define HWRITE2(hp, reg, val) hwrite2(hp, reg, val)
#define HWRITE4(hp, reg, val) \
bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val))
+
#define HCLR1(hp, reg, bits) \
- HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits))
+ do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits)); while (0)
#define HCLR2(hp, reg, bits) \
- HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits))
+ do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits)); while (0)
+#define HCLR4(hp, reg, bits) \
+ do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0)
#define HSET1(hp, reg, bits) \
- HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits))
+ do if (bits) HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits)); while (0)
#define HSET2(hp, reg, bits) \
- HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits))
+ do if (bits) HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits)); while (0)
+#define HSET4(hp, reg, bits) \
+ do if (bits) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0)
static int sdhc_host_reset(sdmmc_chipset_handle_t);
static int sdhc_host_reset1(sdmmc_chipset_handle_t);
@@ -128,8 +178,11 @@
static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *);
static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *);
static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *);
-static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, int);
-static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, int);
+static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int);
+static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int);
+static void esdhc_read_data_pio(struct sdhc_host *, uint8_t *, u_int);
+static void esdhc_write_data_pio(struct sdhc_host *, uint8_t *, u_int);
+
static struct sdmmc_chip_functions sdhc_functions = {
/* host controller reset */
@@ -257,16 +310,23 @@
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