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[src/trunk]: src/sys/arch delete many definitions like MUX_PIN_foo.
details: https://anonhg.NetBSD.org/src/rev/117f94aaead5
branches: trunk
changeset: 778831:117f94aaead5
user: bsh <bsh%NetBSD.org@localhost>
date: Sun Apr 15 10:16:37 2012 +0000
description:
delete many definitions like MUX_PIN_foo.
use MUX_PIN(foo) instead.
diffstat:
sys/arch/arm/imx/imx51_iomuxreg.h | 1003 +----------------------------
sys/arch/evbarm/netwalker/netwalker_usb.c | 27 +-
2 files changed, 29 insertions(+), 1001 deletions(-)
diffs (truncated from 1132 to 300 lines):
diff -r 8166240e9b1f -r 117f94aaead5 sys/arch/arm/imx/imx51_iomuxreg.h
--- a/sys/arch/arm/imx/imx51_iomuxreg.h Sun Apr 15 10:09:58 2012 +0000
+++ b/sys/arch/arm/imx/imx51_iomuxreg.h Sun Apr 15 10:16:37 2012 +0000
@@ -658,996 +658,25 @@
/* MUX & PAD Control */
-#define MUX_PIN_AUD3_BB_CK \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_CK, \
- IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_CK)
-#define MUX_PIN_AUD3_BB_FS \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_FS, \
- IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_FS)
-#define MUX_PIN_AUD3_BB_RXD \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_RXD, \
- IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_RXD)
-#define MUX_PIN_AUD3_BB_TXD \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_TXD, \
- IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_TXD)
-#define MUX_PIN_BOOT_MODE0 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0)
-#define MUX_PIN_BOOT_MODE1 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1)
-#define MUX_PIN_CKIL \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_CKIL)
-#define MUX_PIN_CLK_SS \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_CLK_SS)
-#define MUX_PIN_CSI1_D10 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D10, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D10)
-#define MUX_PIN_CSI1_D11 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D11, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D11)
-#define MUX_PIN_CSI1_D12 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D12, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D12)
-#define MUX_PIN_CSI1_D13 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D13, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D13)
-#define MUX_PIN_CSI1_D14 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D14, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D14)
-#define MUX_PIN_CSI1_D15 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D15, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D15)
-#define MUX_PIN_CSI1_D16 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D16, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D16)
-#define MUX_PIN_CSI1_D17 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D17, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D17)
-#define MUX_PIN_CSI1_D18 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D18, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D18)
-#define MUX_PIN_CSI1_D19 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D19, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D19)
-#define MUX_PIN_CSI1_D8 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D8, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D8)
-#define MUX_PIN_CSI1_D9 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D9, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_D9)
-#define MUX_PIN_CSI1_HSYNC \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_HSYNC, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_HSYNC)
-#define MUX_PIN_CSI1_MCLK \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_CSI1_MCLK)
-#define MUX_PIN_CSI1_PIXCLK \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_CSI1_PIXCLK)
-#define MUX_PIN_CSI1_VSYNC \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_VSYNC, \
- IOMUXC_SW_PAD_CTL_PAD_CSI1_VSYNC)
-#define MUX_PIN_CSI2_D12 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D12, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_D12)
-#define MUX_PIN_CSI2_D13 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D13, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_D13)
-#define MUX_PIN_CSI2_D14 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D14, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_D14)
-#define MUX_PIN_CSI2_D15 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D15, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_D15)
-#define MUX_PIN_CSI2_D16 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D16, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_D16)
-#define MUX_PIN_CSI2_D17 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D17, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_D17)
-#define MUX_PIN_CSI2_D18 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D18, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_D18)
-#define MUX_PIN_CSI2_D19 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D19, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_D19)
-#define MUX_PIN_CSI2_HSYNC \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_HSYNC, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_HSYNC)
-#define MUX_PIN_CSI2_PIXCLK \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_PIXCLK, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_PIXCLK)
-#define MUX_PIN_CSI2_VSYNC \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_VSYNC, \
- IOMUXC_SW_PAD_CTL_PAD_CSI2_VSYNC)
-#define MUX_PIN_CSPI1_MISO \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_MISO, \
- IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO)
-#define MUX_PIN_CSPI1_MOSI \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_MOSI, \
- IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI)
-#define MUX_PIN_CSPI1_RDY \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_RDY, \
- IOMUXC_SW_PAD_CTL_PAD_CSPI1_RDY)
-#define MUX_PIN_CSPI1_SCLK \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_SCLK, \
- IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK)
-#define MUX_PIN_CSPI1_SS0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS0, \
- IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0)
-#define MUX_PIN_CSPI1_SS1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS1, \
- IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1)
-#define MUX_PIN_DI1_D0_CS \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D0_CS, \
- IOMUXC_SW_PAD_CTL_PAD_DI1_D0_CS)
-#define MUX_PIN_DI1_D1_CS \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D1_CS, \
- IOMUXC_SW_PAD_CTL_PAD_DI1_D1_CS)
-#define MUX_PIN_DI1_DISP_CLK \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DI1_DISP_CLK)
-#define MUX_PIN_DI1_PIN11 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN11, \
- IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11)
-#define MUX_PIN_DI1_PIN12 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN12, \
- IOMUXC_SW_PAD_CTL_PAD_DI1_PIN12)
-#define MUX_PIN_DI1_PIN13 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN13, \
- IOMUXC_SW_PAD_CTL_PAD_DI1_PIN13)
-#define MUX_PIN_DI1_PIN15 \
- IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DI1_PIN15)
-#define MUX_PIN_DI1_PIN2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN2, \
- IOMUXC_SW_PAD_CTL_PAD_DI1_PIN2)
-#define MUX_PIN_DI1_PIN3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN3, \
- IOMUXC_SW_PAD_CTL_PAD_DI1_PIN3)
-#define MUX_PIN_DI2_DISP_CLK \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI2_DISP_CLK, \
- IOMUXC_SW_PAD_CTL_PAD_DI2_DISP_CLK)
-#define MUX_PIN_DI2_PIN2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI2_PIN2, \
- IOMUXC_SW_PAD_CTL_PAD_DI2_PIN2)
-#define MUX_PIN_DI2_PIN3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI2_PIN3, \
- IOMUXC_SW_PAD_CTL_PAD_DI2_PIN3)
-#define MUX_PIN_DI2_PIN4 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI2_PIN4, \
- IOMUXC_SW_PAD_CTL_PAD_DI2_PIN4)
-#define MUX_PIN_DISP1_DAT0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT0, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT0)
-#define MUX_PIN_DISP1_DAT1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT1, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT1)
-#define MUX_PIN_DISP1_DAT10 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT10, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT10)
-#define MUX_PIN_DISP1_DAT11 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT11, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT11)
-#define MUX_PIN_DISP1_DAT12 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT12, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT12)
-#define MUX_PIN_DISP1_DAT13 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT13, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT13)
-#define MUX_PIN_DISP1_DAT14 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT14, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT14)
-#define MUX_PIN_DISP1_DAT15 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT15, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT15)
-#define MUX_PIN_DISP1_DAT16 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT16, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT16)
-#define MUX_PIN_DISP1_DAT17 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT17, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT17)
-#define MUX_PIN_DISP1_DAT18 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT18, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT18)
-#define MUX_PIN_DISP1_DAT19 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT19, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT19)
-#define MUX_PIN_DISP1_DAT2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT2, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT2)
-#define MUX_PIN_DISP1_DAT20 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT20, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT20)
-#define MUX_PIN_DISP1_DAT21 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT21, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT21)
-#define MUX_PIN_DISP1_DAT22 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT22, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT22)
-#define MUX_PIN_DISP1_DAT23 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT23, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT23)
-#define MUX_PIN_DISP1_DAT3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT3, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT3)
-#define MUX_PIN_DISP1_DAT4 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT4, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT4)
-#define MUX_PIN_DISP1_DAT5 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT5, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT5)
-#define MUX_PIN_DISP1_DAT6 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT6, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT6)
-#define MUX_PIN_DISP1_DAT7 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT7, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT7)
-#define MUX_PIN_DISP1_DAT8 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT8, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT8)
-#define MUX_PIN_DISP1_DAT9 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT9, \
- IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT9)
-#define MUX_PIN_DISP2_DAT0 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT0, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT0)
-#define MUX_PIN_DISP2_DAT1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT1, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT1)
-#define MUX_PIN_DISP2_DAT10 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT10, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT10)
-#define MUX_PIN_DISP2_DAT11 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT11, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT11)
-#define MUX_PIN_DISP2_DAT12 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT12, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT12)
-#define MUX_PIN_DISP2_DAT13 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT13, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT13)
-#define MUX_PIN_DISP2_DAT14 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT14, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT14)
-#define MUX_PIN_DISP2_DAT15 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT15, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT15)
-#define MUX_PIN_DISP2_DAT2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT2, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT2)
-#define MUX_PIN_DISP2_DAT3 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT3, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT3)
-#define MUX_PIN_DISP2_DAT4 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT4, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT4)
-#define MUX_PIN_DISP2_DAT5 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT5, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT5)
-#define MUX_PIN_DISP2_DAT6 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT6, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT6)
-#define MUX_PIN_DISP2_DAT7 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT7, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT7)
-#define MUX_PIN_DISP2_DAT8 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT8, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT8)
-#define MUX_PIN_DISP2_DAT9 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT9, \
- IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT9)
-#define MUX_PIN_DISPB2_SER_CLK \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_CLK, \
- IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_CLK)
-#define MUX_PIN_DISPB2_SER_DIN \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIN, \
- IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIN)
-#define MUX_PIN_DISPB2_SER_DIO \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIO, \
- IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIO)
-#define MUX_PIN_DISPB2_SER_RS \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_RS, \
- IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_RS)
-#define MUX_PIN_DI_GP1 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP1, \
- IOMUXC_SW_PAD_CTL_PAD_DI_GP1)
-#define MUX_PIN_DI_GP2 \
- IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP2, \
- IOMUXC_SW_PAD_CTL_PAD_DI_GP2)
-#define MUX_PIN_DI_GP3 \
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