Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch PR port-arm/43299: Support added for igepv2/cortexa...
details: https://anonhg.NetBSD.org/src/rev/a9003b0b75ef
branches: trunk
changeset: 755698:a9003b0b75ef
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Wed Jun 16 22:06:53 2010 +0000
description:
PR port-arm/43299: Support added for igepv2/cortexa8/omap3530
Apply patch from PR, with build fixes. ok skrll, matt
diffstat:
sys/arch/arm/arm/cpufunc.c | 227 +++++++++++++++++++++++++--
sys/arch/arm/arm/cpufunc_asm_armv7.S | 160 +++++++++++++++++++
sys/arch/arm/arm32/cortexa8_pmc.c | 149 ++++++++++++++++++
sys/arch/arm/arm32/cpu.c | 6 +-
sys/arch/arm/arm32/db_interface.c | 8 +-
sys/arch/arm/arm32/pmap.c | 108 ++++++++++--
sys/arch/arm/conf/files.arm | 20 +-
sys/arch/arm/include/arm32/pmap.h | 157 +++++++++++++++++--
sys/arch/arm/include/arm32/pte.h | 14 +-
sys/arch/arm/include/armreg.h | 8 +-
sys/arch/arm/include/cpuconf.h | 14 +-
sys/arch/arm/include/cpufunc.h | 28 ++-
sys/arch/arm/omap/omap2_mputmr.c | 8 +-
sys/arch/arm/omap/omap2_obio.c | 10 +-
sys/arch/arm/omap/omap2_reg.h | 17 +-
sys/arch/evbarm/beagle/beagle.h | 6 +-
sys/arch/evbarm/beagle/beagle_machdep.c | 8 +-
sys/arch/evbarm/beagle/beagle_start.S | 30 +--
sys/arch/evbarm/conf/IGEPV2 | 259 ++++++++++++++++++++++++++++++++
sys/arch/evbarm/conf/std.igepv2 | 28 +++
20 files changed, 1154 insertions(+), 111 deletions(-)
diffs (truncated from 2083 to 300 lines):
diff -r 27b919771c6c -r a9003b0b75ef sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c Wed Jun 16 20:15:53 2010 +0000
+++ b/sys/arch/arm/arm/cpufunc.c Wed Jun 16 22:06:53 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.94 2009/12/27 05:14:56 uebayasi Exp $ */
+/* $NetBSD: cpufunc.c,v 1.95 2010/06/16 22:06:53 jmcneill Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -7,6 +7,7 @@
* arm9 support code Copyright (C) 2001 ARM Ltd
* arm11 support code Copyright (c) 2007 Microsoft
* cortexa8 support code Copyright (c) 2008 3am Software Foundry
+ * cortexa8 improvements Copyright (c) Goeran Weinholt
* Copyright (c) 1997 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited
* All rights reserved.
@@ -48,7 +49,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.94 2009/12/27 05:14:56 uebayasi Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.95 2010/06/16 22:06:53 jmcneill Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -98,7 +99,7 @@
int arm_pdcache_size; /* and unified */
int arm_pdcache_line_size;
int arm_pdcache_ways;
-#if (ARM_MMU_V6) != 0
+#if (ARM_MMU_V6 + ARM_MMU_V7) != 0
int arm_cache_prefer_mask;
#endif
@@ -1080,6 +1081,67 @@
#endif
/* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 */
+#if defined(CPU_CORTEXA8)
+struct cpu_functions cortexa8_cpufuncs = {
+ /* CPU functions */
+
+ .cf_id = cpufunc_id,
+ .cf_cpwait = cpufunc_nullop,
+
+ /* MMU functions */
+
+ .cf_control = cpufunc_control,
+ .cf_domains = cpufunc_domains,
+ .cf_setttb = armv7_setttb,
+ .cf_faultstatus = cpufunc_faultstatus,
+ .cf_faultaddress = cpufunc_faultaddress,
+
+ /* TLB functions */
+
+ .cf_tlb_flushID = arm11_tlb_flushID,
+ .cf_tlb_flushID_SE = armv7_tlb_flushID_SE,
+ .cf_tlb_flushI = arm11_tlb_flushI,
+ .cf_tlb_flushI_SE = arm11_tlb_flushI_SE,
+ .cf_tlb_flushD = arm11_tlb_flushD,
+ .cf_tlb_flushD_SE = arm11_tlb_flushD_SE,
+
+ /* Cache operations */
+
+ .cf_icache_sync_all = armv7_icache_sync_all,
+ .cf_dcache_wbinv_all = armv7_dcache_wbinv_all,
+
+ .cf_dcache_inv_range = armv7_dcache_inv_range,
+ .cf_dcache_wb_range = armv7_dcache_wb_range,
+ .cf_dcache_wbinv_range = armv7_dcache_wbinv_range,
+
+ .cf_icache_sync_range = armv7_icache_sync_range,
+ .cf_idcache_wbinv_range = armv7_idcache_wbinv_range,
+
+
+ .cf_idcache_wbinv_all = armv7_idcache_wbinv_all,
+
+ /* Other functions */
+
+ .cf_flush_prefetchbuf = cpufunc_nullop,
+ .cf_drain_writebuf = arm11_drain_writebuf,
+ .cf_flush_brnchtgt_C = cpufunc_nullop,
+ .cf_flush_brnchtgt_E = (void *)cpufunc_nullop,
+
+ .cf_sleep = armv7_cpu_sleep,
+
+ /* Soft functions */
+
+ .cf_dataabt_fixup = cpufunc_null_fixup,
+ .cf_prefetchabt_fixup = cpufunc_null_fixup,
+
+ .cf_context_switch = armv7_context_switch,
+
+ .cf_setup = armv7_setup
+
+};
+#endif /* CPU_CORTEXA8 */
+
+
/*
* Global constants also used by locore.s
*/
@@ -1092,7 +1154,8 @@
defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_ARM11) || \
defined(CPU_FA526) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
- defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)
+ defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
+ defined(CPU_CORTEXA8)
static void get_cachetype_cp15(void);
/* Additional cache information local to this file. Log2 of some of the
@@ -1101,6 +1164,24 @@
static int arm_dcache_l2_assoc;
static int arm_dcache_l2_linesize;
+#if (ARM_MMU_V6 + ARM_MMU_V7) > 0
+static inline u_int
+get_cachesize_cp15(int cssr)
+{
+ u_int csid;
+
+#if (CPU_CORTEXA8) > 0
+ __asm volatile("mcr p15, 2, %0, c0, c0, 0" :: "r" (cssr));
+ /* GAS does not have the ISB instruction ATM */
+ __asm volatile(".word 0xF57FF06F;"); /* sync to the new cssr */
+#else
+ __asm volatile("mcr p15, 1, %0, c0, c0, 2" :: "r" (cssr));
+#endif
+ __asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (csid));
+ return csid;
+}
+#endif
+
static void
get_cachetype_cp15()
{
@@ -1120,15 +1201,13 @@
if (ctype == cpu_id())
goto out;
-#if (ARM_MMU_V6) > 0
+#if (ARM_MMU_V6 + ARM_MMU_V7) > 0
if (CPU_CT_FORMAT(ctype) == 4) {
u_int csid1, csid2;
isize = 1U << (CPU_CT4_ILINE(ctype) + 2);
dsize = 1U << (CPU_CT4_DLINE(ctype) + 2);
- __asm volatile("mcr p15, 1, %0, c0, c0, 2"
- :: "r" (CPU_CSSR_L1)); /* select L1 cache values */
- __asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (csid1));
+ csid1 = get_cachesize_cp15(CPU_CSSR_L1); /* select L1 cache values */
arm_pdcache_ways = CPU_CSID_ASSOC(csid1) + 1;
arm_pdcache_line_size = dsize << CPU_CSID_LEN(csid1);
arm_pdcache_size = arm_pdcache_line_size * arm_pdcache_ways;
@@ -1137,9 +1216,7 @@
arm_dcache_align = arm_pdcache_line_size;
- __asm volatile("mcr p15, 1, %0, c0, c0, 2"
- :: "r" (CPU_CSSR_L2)); /* select L2 cache values */
- __asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (csid2));
+ csid2 = get_cachesize_cp15(CPU_CSSR_L2); /* select L2 cache values */
arm_dcache_l2_assoc = CPU_CSID_ASSOC(csid2) + 1;
arm_dcache_l2_linesize = dsize << CPU_CSID_LEN(csid2);
arm_dcache_l2_nsets = CPU_CSID_NUMSETS(csid2) + 1;
@@ -1169,7 +1246,7 @@
} else {
arm_picache_ways = multiplier <<
(CPU_CT_xSIZE_ASSOC(isize) - 1);
-#if (ARM_MMU_V6) > 0
+#if (ARM_MMU_V6 + ARM_MMU_V7) > 0
if (CPU_CT_xSIZE_P & isize)
arm_cache_prefer_mask |=
__BIT(9 + CPU_CT_xSIZE_SIZE(isize)
@@ -1191,7 +1268,7 @@
} else {
arm_pdcache_ways = multiplier <<
(CPU_CT_xSIZE_ASSOC(dsize) - 1);
-#if (ARM_MMU_V6) > 0
+#if (ARM_MMU_V6 + ARM_MMU_V7) > 0
if (CPU_CT_xSIZE_P & dsize)
arm_cache_prefer_mask |=
__BIT(9 + CPU_CT_xSIZE_SIZE(dsize)
@@ -1412,9 +1489,7 @@
#if defined(CPU_ARM11)
if (cputype == CPU_ID_ARM1136JS ||
cputype == CPU_ID_ARM1136JSR1 ||
- cputype == CPU_ID_ARM1176JS ||
- cputype == CPU_ID_CORTEXA8R1 ||
- cputype == CPU_ID_CORTEXA8R2) {
+ cputype == CPU_ID_ARM1176JS) {
cpufuncs = arm11_cpufuncs;
#if defined(CPU_ARM1136)
if (cputype != CPU_ID_ARM1176JS) {
@@ -1618,6 +1693,21 @@
return 0;
}
#endif /* CPU_XSCALE_IXP425 */
+#if defined(CPU_CORTEXA8)
+ if (cputype == CPU_ID_CORTEXA8R1 ||
+ cputype == CPU_ID_CORTEXA8R2 ||
+ cputype == CPU_ID_CORTEXA8R3) {
+ cpufuncs = cortexa8_cpufuncs;
+ cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
+ cpu_do_powersave = 1; /* Enable powersave */
+ get_cachetype_cp15();
+ pmap_pte_init_armv7();
+ if (arm_cache_prefer_mask)
+ uvmexp.ncolors = (arm_cache_prefer_mask >> PGSHIFT) + 1;
+
+ return 0;
+ }
+#endif /* CPU_CORTEXA8 */
/*
* Bzzzz. And the answer was ...
*/
@@ -2004,7 +2094,7 @@
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_ARM1136) || \
- defined(CPU_FA526)
+ defined(CPU_FA526) || defined(CPU_CORTEXA8)
#define IGN 0
#define OR 1
@@ -2393,7 +2483,7 @@
}
#endif /* CPU_ARM9E || CPU_ARM10 */
-#if defined(CPU_ARM11)
+#if defined(CPU_ARM11)
struct cpu_option arm11_options[] = {
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
@@ -2456,6 +2546,104 @@
}
#endif /* CPU_ARM11 */
+#if defined(CPU_CORTEXA8)
+struct cpu_option armv7_options[] = {
+ { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+ { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+ { "armv7.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+ { "armv7.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
+ { "armv7.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
+ { NULL, IGN, IGN, 0}
+};
+
+void
+armv7_setup(args)
+ char *args;
+{
+ int cpuctrl, cpuctrlmask;
+
+#if defined(PROCESS_ID_IS_CURCPU)
+ /* set curcpu() */
+ __asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&cpu_info_store));
+#elif defined(PROCESS_ID_IS_CURLWP)
+ /* set curlwp() */
+ __asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&lwp0));
+#endif
+
+ cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_IC_ENABLE
+ | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_BPRD_ENABLE ;
+ cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
+ | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
+ | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_BPRD_ENABLE
+ | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
+ | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK;
+
+#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
+ cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
+#endif
+
+ cpuctrl = parse_cpu_options(args, armv7_options, cpuctrl);
+
+#ifdef __ARMEB__
+ cpuctrl |= CPU_CONTROL_BEND_ENABLE;
+#endif
+
+ if (vector_page == ARM_VECTORS_HIGH)
+ cpuctrl |= CPU_CONTROL_VECRELOC;
+
+ /* Clear out the cache */
+ cpu_idcache_wbinv_all();
+ /* set some cortrol register? */
+}
+
+/* Clean the data cache to the level of coherency. Slow. */
+void
+armv7_dcache_wbinv_all()
+{
+ u_int clidr, loc, level;
+
+ /* Cache Level ID Register */
+ __asm volatile("mrc\tp15, 1, %0, c0, c0, 1" : "=r" (clidr));
+
+ loc = (clidr >> 24) & 7; /* Level of Coherency */
Home |
Main Index |
Thread Index |
Old Index