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[src/trunk]: src/sys/arch/powerpc Enable XBSEN and HIGHBAT for OEA 7455 and r...
details: https://anonhg.NetBSD.org/src/rev/81025701a919
branches: trunk
changeset: 773378:81025701a919
user: matt <matt%NetBSD.org@localhost>
date: Wed Feb 01 05:25:57 2012 +0000
description:
Enable XBSEN and HIGHBAT for OEA 7455 and related CPUs.
The BAT entries now have a resolution of 8MB. (Adjacent entries are merged
up to a total of 2GB per entry).
diffstat:
sys/arch/powerpc/include/oea/bat.h | 7 +-
sys/arch/powerpc/include/oea/spr.h | 3 +-
sys/arch/powerpc/oea/cpu_subr.c | 31 ++-
sys/arch/powerpc/oea/genassym.cf | 5 +-
sys/arch/powerpc/oea/oea_machdep.c | 266 +++++++++++++++++++++++--------
sys/arch/powerpc/oea/ofw_rascons.c | 30 ++-
sys/arch/powerpc/oea/pmap.c | 11 +-
sys/arch/powerpc/powerpc/bus_space.c | 47 +++--
sys/arch/powerpc/powerpc/db_interface.c | 93 ++++++----
sys/arch/powerpc/powerpc/trap_subr.S | 45 ++++-
10 files changed, 367 insertions(+), 171 deletions(-)
diffs (truncated from 903 to 300 lines):
diff -r d9231196a93f -r 81025701a919 sys/arch/powerpc/include/oea/bat.h
--- a/sys/arch/powerpc/include/oea/bat.h Wed Feb 01 05:16:56 2012 +0000
+++ b/sys/arch/powerpc/include/oea/bat.h Wed Feb 01 05:25:57 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bat.h,v 1.14 2011/06/20 06:04:33 matt Exp $ */
+/* $NetBSD: bat.h,v 1.15 2012/02/01 05:25:57 matt Exp $ */
/*-
* Copyright (c) 1999 The NetBSD Foundation, Inc.
@@ -126,6 +126,8 @@
#define BAT_BL_2G 0x0000fffc
#define BAT_BL_4G 0x0001fffc
+#define BAT_BL_TO_SIZE(bl) (((bl)+4) << 15)
+
#define BATU(va, len, v) \
(((va) & BAT_EPI) | ((len) & BAT_BL) | ((v) & BAT_V))
@@ -196,7 +198,8 @@
#define BAT601_VALID_P(batl) \
((batl) & BAT601_V)
-#define BAT_VA2IDX(va) ((va) >> ADDR_SR_SHFT)
+#define BAT_VA2IDX(va) ((va) / (8*1024*1024))
+#define BAT_IDX2VA(i) ((i) * (8*1024*1024))
#if defined(_KERNEL) && !defined(_LOCORE)
void oea_batinit(paddr_t, ...);
diff -r d9231196a93f -r 81025701a919 sys/arch/powerpc/include/oea/spr.h
--- a/sys/arch/powerpc/include/oea/spr.h Wed Feb 01 05:16:56 2012 +0000
+++ b/sys/arch/powerpc/include/oea/spr.h Wed Feb 01 05:25:57 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: spr.h,v 1.1 2010/02/25 23:30:05 matt Exp $ */
+/* $NetBSD: spr.h,v 1.2 2012/02/01 05:25:57 matt Exp $ */
#ifndef _POWERPC_OEA_SPR_H_
#define _POWERPC_OEA_SPR_H_
@@ -108,6 +108,7 @@
#define SPR_DBAT6U 0x23c /* ..6. Data BAT Reg 6 Upper */
#define SPR_DBAT6L 0x23d /* ..6. Data BAT Reg 6 Lower */
#define SPR_DBAT7U 0x23e /* ..6. Data BAT Reg 7 Upper */
+#define SPR_DBAT7L 0x23f /* ..6. Data BAT Reg 7 Upper */
#define SPR_UMMCR2 0x3a0 /* ..6. User Monitor Mode Control Register 2 */
#define SPR_UMMCR0 0x3a8 /* ..6. User Monitor Mode Control Register 0 */
#define SPR_USIA 0x3ab /* ..6. User Sampled Instruction Address */
diff -r d9231196a93f -r 81025701a919 sys/arch/powerpc/oea/cpu_subr.c
--- a/sys/arch/powerpc/oea/cpu_subr.c Wed Feb 01 05:16:56 2012 +0000
+++ b/sys/arch/powerpc/oea/cpu_subr.c Wed Feb 01 05:25:57 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_subr.c,v 1.71 2012/01/23 16:22:57 phx Exp $ */
+/* $NetBSD: cpu_subr.c,v 1.72 2012/02/01 05:25:57 matt Exp $ */
/*-
* Copyright (c) 2001 Matt Thomas.
@@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.71 2012/01/23 16:22:57 phx Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.72 2012/02/01 05:25:57 matt Exp $");
#include "opt_ppcparam.h"
#include "opt_multiprocessor.h"
@@ -269,17 +269,27 @@
oeacpufeat = 0;
if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 ||
- vers == IBMCELL || vers == IBMPOWER6P5)
- oeacpufeat |= OEACPU_64 | OEACPU_64_BRIDGE | OEACPU_NOBAT;
+ vers == IBMCELL || vers == IBMPOWER6P5) {
+ oeacpufeat |= OEACPU_64;
+ oeacpufeat |= OEACPU_64_BRIDGE;
+ oeacpufeat |= OEACPU_NOBAT;
- else if (vers == MPC601)
+ } else if (vers == MPC601) {
oeacpufeat |= OEACPU_601;
- else if (MPC745X_P(vers) && vers != MPC7450)
- oeacpufeat |= OEACPU_XBSEN | OEACPU_HIGHBAT | OEACPU_HIGHSPRG;
+ } else if (MPC745X_P(vers) && vers != MPC7450) {
+ oeacpufeat |= OEACPU_HIGHSPRG;
+ oeacpufeat |= OEACPU_XBSEN;
+ oeacpufeat |= OEACPU_HIGHBAT;
+ /* Enable more and larger BAT registers */
+ register_t hid0 = mfspr(SPR_HID0);
+ hid0 |= HID0_XBSEN;
+ hid0 |= HID0_HIGH_BAT_EN;
+ mtspr(SPR_HID0, hid0);
- else if (vers == IBM750FX || vers == IBM750GX)
+ } else if (vers == IBM750FX || vers == IBM750GX) {
oeacpufeat |= OEACPU_HIGHBAT;
+ }
}
void
@@ -525,11 +535,6 @@
/* Enable the 7450 branch caches */
hid0 |= HID0_SGE | HID0_BTIC;
hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
- /* Enable more and larger BAT registers */
- if (oeacpufeat & OEACPU_XBSEN)
- hid0 |= HID0_XBSEN;
- if (oeacpufeat & OEACPU_HIGHBAT)
- hid0 |= HID0_HIGH_BAT_EN;
/* Disable BTIC on 7450 Rev 2.0 or earlier */
if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
hid0 &= ~HID0_BTIC;
diff -r d9231196a93f -r 81025701a919 sys/arch/powerpc/oea/genassym.cf
--- a/sys/arch/powerpc/oea/genassym.cf Wed Feb 01 05:16:56 2012 +0000
+++ b/sys/arch/powerpc/oea/genassym.cf Wed Feb 01 05:25:57 2012 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.25 2011/06/20 19:56:12 matt Exp $
+# $NetBSD: genassym.cf,v 1.26 2012/02/01 05:25:57 matt Exp $
#
# Copyright (C) 1995, 1996 Wolfgang Solfrank.
@@ -46,6 +46,7 @@
include <machine/pmap.h>
include <powerpc/cpu.h>
+include <powerpc/oea/bat.h>
include <powerpc/oea/cpufeat.h>
define FRAME_DAR offsetof(struct ktrapframe, ktf_tf.tf_dar)
@@ -85,6 +86,8 @@
define OEACPU_HIGHSPRG OEACPU_HIGHSPRG
define OEACPU_ALTIVEC OEACPU_ALTIVEC
+define BAT_ADDR_SHIFT ilog2(BAT_IDX2VA(1))
+
define PTE_REF PTE_REF
define PTE_CHG PTE_CHG
define PTE_HID PTE_HID
diff -r d9231196a93f -r 81025701a919 sys/arch/powerpc/oea/oea_machdep.c
--- a/sys/arch/powerpc/oea/oea_machdep.c Wed Feb 01 05:16:56 2012 +0000
+++ b/sys/arch/powerpc/oea/oea_machdep.c Wed Feb 01 05:25:57 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: oea_machdep.c,v 1.60 2011/07/17 20:54:46 joerg Exp $ */
+/* $NetBSD: oea_machdep.c,v 1.61 2012/02/01 05:25:57 matt Exp $ */
/*
* Copyright (C) 2002 Matt Thomas
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.60 2011/07/17 20:54:46 joerg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: oea_machdep.c,v 1.61 2012/02/01 05:25:57 matt Exp $");
#include "opt_ppcarch.h"
#include "opt_compat_netbsd.h"
@@ -81,10 +81,10 @@
#include <powerpc/altivec.h>
#include <powerpc/pcb.h>
+#include <powerpc/oea/bat.h>
+#include <powerpc/oea/cpufeat.h>
#include <powerpc/oea/spr.h>
-#include <powerpc/oea/bat.h>
#include <powerpc/oea/sr_601.h>
-#include <powerpc/oea/cpufeat.h>
char machine[] = MACHINE; /* from <machine/param.h> */
char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */
@@ -97,13 +97,18 @@
static void trap0(void *);
/* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */
-struct bat battable[512];
+struct bat battable[BAT_VA2IDX(0xffffffff)+1];
register_t iosrtable[16]; /* I/O segments, for kernel_pmap setup */
#ifndef MSGBUFADDR
paddr_t msgbuf_paddr;
#endif
+extern int dsitrap_fix_dbat4[];
+extern int dsitrap_fix_dbat5[];
+extern int dsitrap_fix_dbat6[];
+extern int dsitrap_fix_dbat7[];
+
void
oea_init(void (*handler)(void))
{
@@ -362,6 +367,8 @@
*/
__syncicache((void *) trapstart,
(uintptr_t) trapend - (uintptr_t) trapstart);
+ __syncicache(dsitrap_fix_dbat4, 16);
+ __syncicache(dsitrap_fix_dbat7, 8);
#ifdef PPC_OEA601
/*
@@ -449,35 +456,69 @@
#endif /* PPC_OEA601 */
#if defined (PPC_OEA) || defined (PPC_OEA64_BRIDGE)
+#define DBAT_SET(n, batl, batu) \
+ do { \
+ mtspr(SPR_DBAT##n##L, (batl)); \
+ mtspr(SPR_DBAT##n##U, (batu)); \
+ } while (/*CONSTCOND*/ 0)
+#define DBAT_RESET(n) DBAT_SET(n, 0, 0)
+#define DBATU_GET(n) mfspr(SPR_DBAT##n##U)
+#define IBAT_SET(n, batl, batu) \
+ do { \
+ mtspr(SPR_IBAT##n##L, (batl)); \
+ mtspr(SPR_IBAT##n##U, (batu)); \
+ } while (/*CONSTCOND*/ 0)
+#define IBAT_RESET(n) IBAT_SET(n, 0, 0)
+
void
oea_iobat_add(paddr_t pa, register_t len)
{
- static int n = 1;
- const u_int i = pa >> 28;
- battable[i].batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW);
- battable[i].batu = BATU(pa, len, BAT_Vs);
+ static int z = 1;
+ const u_int n = __SHIFTOUT(len, (BAT_XBL|BAT_BL) & ~BAT_BL_8M);
+ const u_int i = BAT_VA2IDX(pa) & -n; /* in case pa was in the middle */
+ const int after_bat3 = (oeacpufeat & OEACPU_HIGHBAT) ? 4 : 8;
+
+ KASSERT(len >= BAT_BL_8M);
+
+ const register_t batl = BATL(pa, BAT_I|BAT_G, BAT_PP_RW);
+ const register_t batu = BATU(pa, len, BAT_Vs);
+
+ for (u_int j = 0; j < n; j++) {
+ battable[i + j].batl = batl;
+ battable[i + j].batu = batu;
+ }
/*
* Let's start loading the BAT registers.
*/
- switch (n) {
+ switch (z) {
case 1:
- __asm volatile ("mtdbatl 1,%0; mtdbatu 1,%1;"
- :: "r"(battable[i].batl),
- "r"(battable[i].batu));
- n = 2;
+ DBAT_SET(1, batl, batu);
+ z = 2;
break;
case 2:
- __asm volatile ("mtdbatl 2,%0; mtdbatu 2,%1;"
- :: "r"(battable[i].batl),
- "r"(battable[i].batu));
- n = 3;
+ DBAT_SET(2, batl, batu);
+ z = 3;
break;
case 3:
- __asm volatile ("mtdbatl 3,%0; mtdbatu 3,%1;"
- :: "r"(battable[i].batl),
- "r"(battable[i].batu));
- n = 4;
+ DBAT_SET(3, batl, batu);
+ z = after_bat3; /* no highbat, skip to end */
+ break;
+ case 4:
+ DBAT_SET(4, batl, batu);
+ z = 5;
+ break;
+ case 5:
+ DBAT_SET(5, batl, batu);
+ z = 6;
+ break;
+ case 6:
+ DBAT_SET(6, batl, batu);
+ z = 7;
+ break;
+ case 7:
+ DBAT_SET(7, batl, batu);
+ z = 8;
break;
default:
break;
@@ -487,38 +528,63 @@
void
oea_iobat_remove(paddr_t pa)
{
- register_t batu;
- int i, n;
+ const u_int i = BAT_VA2IDX(pa);
- n = pa >> ADDR_SR_SHFT;
- if (!BAT_VA_MATCH_P(battable[n].batu, pa) ||
- !BAT_VALID_P(battable[n].batu, PSL_PR))
+ if (!BAT_VA_MATCH_P(battable[i].batu, pa) ||
+ !BAT_VALID_P(battable[i].batu, PSL_PR))
return;
- battable[n].batl = 0;
- battable[n].batu = 0;
-#define BAT_RESET(n) \
- __asm volatile("mtdbatu %0,%1; mtdbatl %0,%1" :: "n"(n), "r"(0))
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