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[src/trunk]: src/sys/arch driver for i.MX51 Clock Controller Module.
details: https://anonhg.NetBSD.org/src/rev/58d4a554d9e6
branches: trunk
changeset: 778853:58d4a554d9e6
user: bsh <bsh%NetBSD.org@localhost>
date: Tue Apr 17 09:33:31 2012 +0000
description:
driver for i.MX51 Clock Controller Module.
from Kenichi Hashimoto.
Currently used only to get peripheral clock frequencies.
diffstat:
sys/arch/arm/imx/imx51_axi.c | 6 +-
sys/arch/arm/imx/imx51_ccm.c | 425 +++++++++++++++++++++++++++++++++++++++
sys/arch/arm/imx/imx51_ccmreg.h | 199 ++++++++++++++++++
sys/arch/arm/imx/imx51_ccmvar.h | 78 +++++++
sys/arch/arm/imx/imx51_clock.c | 16 +-
sys/arch/arm/imx/imx51_dpllreg.h | 62 +++++
sys/arch/arm/imx/imxclock.c | 19 +-
sys/arch/arm/imx/imxclockvar.h | 2 +
sys/arch/evbarm/conf/NETWALKER | 6 +-
9 files changed, 793 insertions(+), 20 deletions(-)
diffs (truncated from 951 to 300 lines):
diff -r 969d4a7b60be -r 58d4a554d9e6 sys/arch/arm/imx/imx51_axi.c
--- a/sys/arch/arm/imx/imx51_axi.c Tue Apr 17 09:23:21 2012 +0000
+++ b/sys/arch/arm/imx/imx51_axi.c Tue Apr 17 09:33:31 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_axi.c,v 1.2 2010/11/30 13:05:27 bsh Exp $ */
+/* $NetBSD: imx51_axi.c,v 1.3 2012/04/17 09:33:31 bsh Exp $ */
/*-
* Copyright (c) 2010 SHIMIZU Ryo <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_axi.c,v 1.2 2010/11/30 13:05:27 bsh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_axi.c,v 1.3 2012/04/17 09:33:31 bsh Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -38,6 +38,7 @@
#include <arm/imx/imx51reg.h>
#include <arm/imx/imx51var.h>
+#include "bus_dma_generic.h"
#include "locators.h"
struct axi_softc {
@@ -102,6 +103,7 @@
if ((strcmp(cf->cf_name, "tzic") != 0) &&
(strcmp(cf->cf_name, "imxuart") != 0) &&
+ (strcmp(cf->cf_name, "imxccm") != 0) &&
(strcmp(cf->cf_name, "imxgpio") != 0))
return 0;
diff -r 969d4a7b60be -r 58d4a554d9e6 sys/arch/arm/imx/imx51_ccm.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imx51_ccm.c Tue Apr 17 09:33:31 2012 +0000
@@ -0,0 +1,425 @@
+/* $NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $ */
+/*
+ * Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Clock Controller Module (CCM)
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $");
+
+#include <sys/types.h>
+#include <sys/time.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/param.h>
+
+#include <machine/cpu.h>
+
+#include <arm/imx/imx51_ccmvar.h>
+#include <arm/imx/imx51_ccmreg.h>
+#include <arm/imx/imx51_dpllreg.h>
+
+#include <arm/imx/imx51var.h>
+#include <arm/imx/imx51reg.h>
+
+#include "opt_imx51clk.h"
+#include "locators.h"
+
+//#define IMXCCMDEBUG
+
+#ifndef IMX51_OSC_FREQ
+#define IMX51_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */
+#endif
+
+struct imxccm_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh;
+
+ struct {
+ bus_space_handle_t pll_ioh;
+ u_int pll_freq;
+ } sc_pll[IMX51_N_DPLLS];
+};
+
+struct imxccm_softc *ccm_softc;
+
+static uint64_t imx51_get_pll_freq(u_int);
+
+static int imxccm_match(device_t, cfdata_t, void *);
+static void imxccm_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(imxccm, sizeof(struct imxccm_softc),
+ imxccm_match, imxccm_attach, NULL, NULL);
+
+static int
+imxccm_match(device_t parent, cfdata_t cfdata, void *aux)
+{
+ struct axi_attach_args *aa = aux;
+
+ if (aa->aa_addr == CCMC_BASE)
+ return 1;
+
+ return 0;
+}
+
+static void
+imxccm_attach(device_t parent, device_t self, void *aux)
+{
+ struct axi_attach_args *aa = aux;
+ bus_space_tag_t iot = aa->aa_iot;
+ int i;
+
+ ccm_softc = device_private(self);
+ ccm_softc->sc_dev = self;
+ ccm_softc->sc_iot = iot;
+
+ if (bus_space_map(iot, aa->aa_addr, CCMC_SIZE, 0,
+ &ccm_softc->sc_ioh)) {
+ aprint_error(": can't map\n");
+ return;
+ }
+
+ for (i=1; i <= IMX51_N_DPLLS; ++i) {
+ if (bus_space_map(iot, DPLL_BASE(i), DPLL_SIZE, 0,
+ &ccm_softc->sc_pll[i-1].pll_ioh)) {
+ aprint_error(": can't map\n");
+ return;
+ }
+ }
+
+ aprint_normal(": Clock control module\n");
+ aprint_naive("\n");
+
+ imx51_get_pll_freq(1);
+ imx51_get_pll_freq(2);
+ imx51_get_pll_freq(3);
+
+
+ aprint_verbose_dev(self, "CPU clock=%d, UART clock=%d\n",
+ imx51_get_clock(IMX51CLK_ARM_ROOT),
+ imx51_get_clock(IMX51CLK_UART_CLK_ROOT));
+ aprint_verbose_dev(self,
+ "mainbus clock=%d, ahb clock=%d ipg clock=%d perclk=%d\n",
+ imx51_get_clock(IMX51CLK_MAIN_BUS_CLK),
+ imx51_get_clock(IMX51CLK_AHB_CLK_ROOT),
+ imx51_get_clock(IMX51CLK_IPG_CLK_ROOT),
+ imx51_get_clock(IMX51CLK_PERCLK_ROOT));
+}
+
+
+u_int
+imx51_get_clock(enum imx51_clock clk)
+{
+ bus_space_tag_t iot = ccm_softc->sc_iot;
+ bus_space_handle_t ioh = ccm_softc->sc_ioh;
+
+ u_int freq;
+ u_int sel;
+ uint32_t cacrr; /* ARM clock root register */
+ uint32_t ccsr;
+ uint32_t cscdr1;
+ uint32_t cscmr1;
+ uint32_t cbcdr;
+ uint32_t cbcmr;
+ uint32_t cdcr;
+
+ switch (clk) {
+ case IMX51CLK_PLL1:
+ case IMX51CLK_PLL2:
+ case IMX51CLK_PLL3:
+ return ccm_softc->sc_pll[clk-IMX51CLK_PLL1].pll_freq;
+ case IMX51CLK_PLL1SW:
+ ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
+ if ((ccsr & CCSR_PLL1_SW_CLK_SEL) == 0)
+ return ccm_softc->sc_pll[1-1].pll_freq;
+ /* step clock */
+ /* FALLTHROUGH */
+ case IMX51CLK_PLL1STEP:
+ ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
+ switch ((ccsr & CCSR_STEP_SEL_MASK) >> CCSR_STEP_SEL_SHIFT) {
+ case 0:
+ return imx51_get_clock(IMX51CLK_LP_APM);
+ case 1:
+ return 0; /* XXX PLL bypass clock */
+ case 2:
+ return ccm_softc->sc_pll[2-1].pll_freq /
+ (1 + ((ccsr & CCSR_PLL2_DIV_PODF_MASK) >>
+ CCSR_PLL2_DIV_PODF_SHIFT));
+ case 3:
+ return ccm_softc->sc_pll[3-1].pll_freq /
+ (1 + ((ccsr & CCSR_PLL3_DIV_PODF_MASK) >>
+ CCSR_PLL3_DIV_PODF_SHIFT));
+ }
+ /*NOTREACHED*/
+ case IMX51CLK_PLL2SW:
+ ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
+ if ((ccsr & CCSR_PLL2_SW_CLK_SEL) == 0)
+ return imx51_get_clock(IMX51CLK_PLL2);
+ return 0; /* XXX PLL2 bypass clk */
+ case IMX51CLK_PLL3SW:
+ ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
+ if ((ccsr & CCSR_PLL3_SW_CLK_SEL) == 0)
+ return imx51_get_clock(IMX51CLK_PLL3);
+ return 0; /* XXX PLL3 bypass clk */
+
+ case IMX51CLK_LP_APM:
+ ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
+ return (ccsr & CCSR_LP_APM) ?
+ imx51_get_clock(IMX51CLK_FPM) : IMX51_OSC_FREQ;
+
+ case IMX51CLK_ARM_ROOT:
+ freq = imx51_get_clock(IMX51CLK_PLL1SW);
+ cacrr = bus_space_read_4(iot, ioh, CCMC_CACRR);
+ return freq / (cacrr + 1);
+
+ /* ... */
+ case IMX51CLK_MAIN_BUS_CLK_SRC:
+ cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
+ if ((cbcdr & CBCDR_PERIPH_CLK_SEL) == 0)
+ freq = imx51_get_clock(IMX51CLK_PLL2SW);
+ else {
+ freq = 0;
+ cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
+ switch ((cbcmr & CBCMR_PERIPH_APM_SEL_MASK) >>
+ CBCMR_PERIPH_APM_SEL_SHIFT) {
+ case 0:
+ freq = imx51_get_clock(IMX51CLK_PLL1SW);
+ break;
+ case 1:
+ freq = imx51_get_clock(IMX51CLK_PLL3SW);
+ break;
+ case 2:
+ freq = imx51_get_clock(IMX51CLK_LP_APM);
+ break;
+ case 3:
+ /* XXX: error */
+ break;
+ }
+ }
+ return freq;
+ case IMX51CLK_MAIN_BUS_CLK:
+ freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC);
+ cdcr = bus_space_read_4(iot, ioh, CCMC_CDCR);
+ return freq / (cdcr & CDCR_PERIPH_CLK_DVFS_PODF_MASK) >>
+ CDCR_PERIPH_CLK_DVFS_PODF_SHIFT;
+ case IMX51CLK_AHB_CLK_ROOT:
+ freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK);
+ cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
+ return freq / (1 + ((cbcdr & CBCDR_AHB_PODF_MASK) >>
+ CBCDR_AHB_PODF_SHIFT));
+ case IMX51CLK_IPG_CLK_ROOT:
+ freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT);
+ cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
+ return freq / (1 + ((cbcdr & CBCDR_IPG_PODF_MASK) >>
+ CBCDR_IPG_PODF_SHIFT));
+
+ case IMX51CLK_PERCLK_ROOT:
+ cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
+ if (cbcmr & CBCMR_PERCLK_IPG_SEL)
+ return imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
+ if (cbcmr & CBCMR_PERCLK_LP_APM_SEL)
+ freq = imx51_get_clock(IMX51CLK_LP_APM);
+ else
+ freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC);
+ cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
+
+#ifdef IMXCCMDEBUG
+ printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr);
+#endif
+
+ freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED1_MASK) >>
+ CBCDR_PERCLK_PRED1_SHIFT);
+ freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED2_MASK) >>
+ CBCDR_PERCLK_PRED2_SHIFT);
+ freq /= 1 + ((cbcdr & CBCDR_PERCLK_PODF_MASK) >>
+ CBCDR_PERCLK_PODF_SHIFT);
+ return freq;
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