[src/trunk]: src/sys/arch Add write-through cache work-around for ARM11 as we...

[uebayasi <uebayasi%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/b82e03dbb11e
branches:  trunk
changeset: 750351:b82e03dbb11e
user:      uebayasi <uebayasi%NetBSD.org@localhost>
date:      Sun Dec 27 05:14:56 2009 +0000

description:
Add write-through cache work-around for ARM11 as well as ARM9/ARM10.  Analyzed
& tested on i.MX35 with help from Tsubai Masanari.

diffstat:

 sys/arch/arm/arm/cpufunc.c        |   8 ++++++--
 sys/arch/arm/arm32/pmap.c         |  27 ++++++++++++++++++++++++---
 sys/arch/arm/conf/files.arm       |   3 ++-
 sys/arch/arm/include/arm32/pmap.h |   5 ++++-
 sys/arch/evbarm/conf/std.imx31    |   3 ++-
 5 files changed, 38 insertions(+), 8 deletions(-)

diffs (138 lines):

diff -r 9c58c3c63b0c -r b82e03dbb11e sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c        Sun Dec 27 01:44:13 2009 +0000
+++ b/sys/arch/arm/arm/cpufunc.c        Sun Dec 27 05:14:56 2009 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc.c,v 1.93 2009/03/15 22:23:16 cegger Exp $      */
+/*     $NetBSD: cpufunc.c,v 1.94 2009/12/27 05:14:56 uebayasi Exp $    */
 
 /*
  * arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -48,7 +48,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.93 2009/03/15 22:23:16 cegger Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.94 2009/12/27 05:14:56 uebayasi Exp $");
 
 #include "opt_compat_netbsd.h"
 #include "opt_cpuoptions.h"
@@ -1426,7 +1426,11 @@
                cpu_reset_needs_v4_MMU_disable = 1;     /* V4 or higher */
                cpu_do_powersave = 1;                   /* Enable powersave */
                get_cachetype_cp15();
+#ifdef ARM11_CACHE_WRITE_THROUGH
+               pmap_pte_init_arm11();
+#else
                pmap_pte_init_generic();
+#endif
                if (arm_cache_prefer_mask)
                        uvmexp.ncolors = (arm_cache_prefer_mask >> PGSHIFT) + 1;
 
diff -r 9c58c3c63b0c -r b82e03dbb11e sys/arch/arm/arm32/pmap.c
--- a/sys/arch/arm/arm32/pmap.c Sun Dec 27 01:44:13 2009 +0000
+++ b/sys/arch/arm/arm32/pmap.c Sun Dec 27 05:14:56 2009 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.c,v 1.203 2009/11/28 11:44:45 scw Exp $   */
+/*     $NetBSD: pmap.c,v 1.204 2009/12/27 05:14:56 uebayasi Exp $      */
 
 /*
  * Copyright 2003 Wasabi Systems, Inc.
@@ -211,7 +211,7 @@
 #include <machine/param.h>
 #include <arm/arm32/katelib.h>
 
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.203 2009/11/28 11:44:45 scw Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.204 2009/12/27 05:14:56 uebayasi Exp $");
 
 #ifdef PMAP_DEBUG
 
@@ -5971,7 +5971,7 @@
        pte_l2_l_cache_mode_pt = L2_C;
        pte_l2_s_cache_mode_pt = L2_C;
 }
-#endif /* CPU_ARM9 */
+#endif /* CPU_ARM9 && ARM9_CACHE_WRITE_THROUGH */
 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6) != 0 */
 
 #if defined(CPU_ARM10)
@@ -5996,6 +5996,27 @@
 }
 #endif /* CPU_ARM10 */
 
+#if defined(CPU_ARM11) && defined(ARM11_CACHE_WRITE_THROUGH)
+void
+pmap_pte_init_arm11(void)
+{
+
+       /*
+        * ARM11 is compatible with generic, but we want to use
+        * write-through caching for now.
+        */
+       pmap_pte_init_generic();
+
+       pte_l1_s_cache_mode = L1_S_C;
+       pte_l2_l_cache_mode = L2_C;
+       pte_l2_s_cache_mode = L2_C;
+
+       pte_l1_s_cache_mode_pt = L1_S_C;
+       pte_l2_l_cache_mode_pt = L2_C;
+       pte_l2_s_cache_mode_pt = L2_C;
+}
+#endif /* CPU_ARM11 && ARM11_CACHE_WRITE_THROUGH */
+
 #if ARM_MMU_SA1 == 1
 void
 pmap_pte_init_sa1(void)
diff -r 9c58c3c63b0c -r b82e03dbb11e sys/arch/arm/conf/files.arm
--- a/sys/arch/arm/conf/files.arm       Sun Dec 27 01:44:13 2009 +0000
+++ b/sys/arch/arm/conf/files.arm       Sun Dec 27 05:14:56 2009 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: files.arm,v 1.96 2009/01/18 16:42:09 bjh21 Exp $
+#      $NetBSD: files.arm,v 1.97 2009/12/27 05:14:56 uebayasi Exp $
 
 # temporary define to allow easy moving to ../arch/arm/arm32
 defflag                                ARM32
@@ -27,6 +27,7 @@
 defflag  opt_cpuoptions.h      PROCESS_ID_IS_CURLWP
 defflag  opt_cpuoptions.h      PROCESS_ID_IS_CURCPU
 defflag  opt_cpuoptions.h      ARM11_PMC
+defflag  opt_cpuoptions.h      ARM11_CACHE_WRITE_THROUGH
 
 # Interrupt implementation header definition.
 defparam opt_arm_intr_impl.h   ARM_INTR_IMPL
diff -r 9c58c3c63b0c -r b82e03dbb11e sys/arch/arm/include/arm32/pmap.h
--- a/sys/arch/arm/include/arm32/pmap.h Sun Dec 27 01:44:13 2009 +0000
+++ b/sys/arch/arm/include/arm32/pmap.h Sun Dec 27 05:14:56 2009 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.h,v 1.93 2009/10/22 19:50:55 rmind Exp $  */
+/*     $NetBSD: pmap.h,v 1.94 2009/12/27 05:14:56 uebayasi Exp $       */
 
 /*
  * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@@ -462,6 +462,9 @@
 #if defined(CPU_ARM10)
 void   pmap_pte_init_arm10(void);
 #endif /* CPU_ARM10 */
+#if defined(CPU_ARM11)
+void   pmap_pte_init_arm11(void);
+#endif /* CPU_ARM11 */
 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
 
 #if ARM_MMU_SA1 == 1
diff -r 9c58c3c63b0c -r b82e03dbb11e sys/arch/evbarm/conf/std.imx31
--- a/sys/arch/evbarm/conf/std.imx31    Sun Dec 27 01:44:13 2009 +0000
+++ b/sys/arch/evbarm/conf/std.imx31    Sun Dec 27 05:14:56 2009 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: std.imx31,v 1.2 2008/04/27 18:58:46 matt Exp $
+#      $NetBSD: std.imx31,v 1.3 2009/12/27 05:14:56 uebayasi Exp $
 #
 # standard NetBSD/evbarm options for FreeScale I.MX31 
 
@@ -17,6 +17,7 @@
 # To support easy transit to ../arch/arm/arm32
 options        ARM32
 options        ARM11_PMC
+options        ARM11_CACHE_WRITE_THROUGH
 
 makeoptions    LOADADDRESS="0x80100000"
 makeoptions    BOARDTYPE="imx31"