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[src/trunk]: src/sys/arch Move the standard definitions of the {UND, IRQ, FIQ, A...
details: https://anonhg.NetBSD.org/src/rev/dc4dc50eb384
branches: trunk
changeset: 781063:dc4dc50eb384
user: matt <matt%NetBSD.org@localhost>
date: Thu Aug 16 18:22:37 2012 +0000
description:
Move the standard definitions of the {UND,IRQ,FIQ,ABT}_STACK_SIZE to
<arm32/machdep.h>
Move the extern for cpu_reset_address to the same file.
Add cpu_reset_address_paddr.
Kill cpu_reset_v4_MMU_disable.
if cpu_reset_address is NULL, then the MMU will be disabled.
diffstat:
sys/arch/acorn32/acorn32/rpc_machdep.c | 17 +---------
sys/arch/acorn32/eb7500atx/eb7500atx_machdep.c | 12 +------
sys/arch/arm/arm/cpufunc.c | 28 +----------------
sys/arch/arm/arm32/arm32_machdep.c | 8 ++--
sys/arch/arm/arm32/locore.S | 38 +++++++++--------------
sys/arch/arm/include/arm32/machdep.h | 24 ++++++++++++++-
sys/arch/cats/cats/cats_machdep.c | 13 ++-----
sys/arch/evbarm/adi_brh/brh_machdep.c | 17 +---------
sys/arch/evbarm/armadillo/armadillo9_machdep.c | 21 ++++--------
sys/arch/evbarm/g42xxeb/g42xxeb_machdep.c | 16 +---------
sys/arch/evbarm/gemini/gemini_machdep.c | 22 +------------
sys/arch/evbarm/gumstix/gumstix_machdep.c | 16 +---------
sys/arch/evbarm/hdl_g/hdlg_machdep.c | 19 +----------
sys/arch/evbarm/imx31/imx31lk_machdep.c | 22 +------------
sys/arch/evbarm/integrator/integrator_machdep.c | 19 ++---------
sys/arch/evbarm/iq80310/iq80310_machdep.c | 17 +---------
sys/arch/evbarm/iq80321/iq80321_machdep.c | 20 +-----------
sys/arch/evbarm/ixdp425/ixdp425_machdep.c | 18 +----------
sys/arch/evbarm/ixm1200/ixm1200_machdep.c | 13 ++-----
sys/arch/evbarm/lubbock/lubbock_machdep.c | 18 +----------
sys/arch/evbarm/marvell/marvell_machdep.c | 23 ++------------
sys/arch/evbarm/mini2440/mini2440_machdep.c | 16 +--------
sys/arch/evbarm/mmnet/mmnet_machdep.c | 15 +-------
sys/arch/evbarm/mpcsa/mpcsa_machdep.c | 15 +-------
sys/arch/evbarm/netwalker/netwalker_machdep.c | 23 +-------------
sys/arch/evbarm/npwr_fc/npwr_fc_machdep.c | 20 +-----------
sys/arch/evbarm/nslu2/nslu2_machdep.c | 18 +----------
sys/arch/evbarm/osk5912/osk5912_machdep.c | 18 +----------
sys/arch/evbarm/rpi/rpi_machdep.c | 22 +------------
sys/arch/evbarm/smdk2xx0/smdk2410_machdep.c | 19 +----------
sys/arch/evbarm/smdk2xx0/smdk2800_machdep.c | 19 +----------
sys/arch/evbarm/tisdp24xx/sdp24xx_machdep.c | 22 +------------
sys/arch/evbarm/tsarm/tsarm_machdep.c | 22 ++++---------
sys/arch/evbarm/viper/viper_machdep.c | 18 +----------
sys/arch/hpcarm/hpcarm/pxa2x0_hpc_machdep.c | 17 +---------
sys/arch/hpcarm/hpcarm/sa11x0_hpc_machdep.c | 17 +---------
sys/arch/iyonix/iyonix/iyonix_machdep.c | 20 +-----------
sys/arch/netwinder/netwinder/netwinder_machdep.c | 17 +--------
sys/arch/zaurus/zaurus/machdep.c | 16 +--------
39 files changed, 136 insertions(+), 599 deletions(-)
diffs (truncated from 1814 to 300 lines):
diff -r 149061c30371 -r dc4dc50eb384 sys/arch/acorn32/acorn32/rpc_machdep.c
--- a/sys/arch/acorn32/acorn32/rpc_machdep.c Thu Aug 16 18:16:25 2012 +0000
+++ b/sys/arch/acorn32/acorn32/rpc_machdep.c Thu Aug 16 18:22:37 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: rpc_machdep.c,v 1.84 2012/07/29 00:07:10 matt Exp $ */
+/* $NetBSD: rpc_machdep.c,v 1.85 2012/08/16 18:22:37 matt Exp $ */
/*
* Copyright (c) 2000-2002 Reinoud Zandijk.
@@ -55,7 +55,7 @@
#include <sys/param.h>
-__KERNEL_RCSID(0, "$NetBSD: rpc_machdep.c,v 1.84 2012/07/29 00:07:10 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rpc_machdep.c,v 1.85 2012/08/16 18:22:37 matt Exp $");
#include <sys/systm.h>
#include <sys/kernel.h>
@@ -115,19 +115,6 @@
*/
#define KERNEL_VM_SIZE 0x05000000
-/*
- * Address to call from cpu_reset() to reset the machine.
- * This is machine architecture dependent as it varies depending
- * on where the ROM appears when you turn the MMU off.
- */
-u_int cpu_reset_address = 0x0; /* XXX 0x3800000 too for rev0 RiscPC 600 */
-
-/* Define various stack sizes in pages */
-#define IRQ_STACK_SIZE 1
-#define ABT_STACK_SIZE 1
-#define UND_STACK_SIZE 1
-
-
struct bootconfig bootconfig; /* Boot config storage */
videomemory_t videomemory; /* Video memory descriptor */
diff -r 149061c30371 -r dc4dc50eb384 sys/arch/acorn32/eb7500atx/eb7500atx_machdep.c
--- a/sys/arch/acorn32/eb7500atx/eb7500atx_machdep.c Thu Aug 16 18:16:25 2012 +0000
+++ b/sys/arch/acorn32/eb7500atx/eb7500atx_machdep.c Thu Aug 16 18:22:37 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: eb7500atx_machdep.c,v 1.23 2012/07/29 00:07:10 matt Exp $ */
+/* $NetBSD: eb7500atx_machdep.c,v 1.24 2012/08/16 18:22:38 matt Exp $ */
/*
* Copyright (c) 2000-2002 Reinoud Zandijk.
@@ -55,7 +55,7 @@
#include <sys/param.h>
-__KERNEL_RCSID(0, "$NetBSD: eb7500atx_machdep.c,v 1.23 2012/07/29 00:07:10 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: eb7500atx_machdep.c,v 1.24 2012/08/16 18:22:38 matt Exp $");
#include <sys/systm.h>
#include <sys/kernel.h>
@@ -119,17 +119,9 @@
* This is machine architecture dependent as it varies depending
* on where the ROM appears when you turn the MMU off.
*/
-u_int cpu_reset_address = 0x0; /* XXX 0x3800000 too for rev0 RiscPC 600 */
#define VERBOSE_INIT_ARM
-
-/* Define various stack sizes in pages */
-#define IRQ_STACK_SIZE 1
-#define ABT_STACK_SIZE 1
-#define UND_STACK_SIZE 1
-
-
struct bootconfig bootconfig; /* Boot config storage */
videomemory_t videomemory; /* Video memory descriptor */
diff -r 149061c30371 -r dc4dc50eb384 sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c Thu Aug 16 18:16:25 2012 +0000
+++ b/sys/arch/arm/arm/cpufunc.c Thu Aug 16 18:22:37 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.109 2012/07/23 15:51:48 skrll Exp $ */
+/* $NetBSD: cpufunc.c,v 1.110 2012/08/16 18:22:38 matt Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.109 2012/07/23 15:51:48 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.110 2012/08/16 18:22:38 matt Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -1322,7 +1322,6 @@
struct cpu_functions cpufuncs;
u_int cputype;
-u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
#if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_ARM11) || \
@@ -1555,7 +1554,6 @@
#ifdef CPU_ARM2
if (cputype == CPU_ID_ARM2) {
cpufuncs = arm2_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 0;
get_cachetype_table();
return 0;
}
@@ -1563,7 +1561,6 @@
#ifdef CPU_ARM250
if (cputype == CPU_ID_ARM250) {
cpufuncs = arm250_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 0;
get_cachetype_table();
return 0;
}
@@ -1572,7 +1569,6 @@
if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD &&
(cputype & 0x00000f00) == 0x00000300) {
cpufuncs = arm3_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 0;
get_cachetype_table();
return 0;
}
@@ -1581,7 +1577,6 @@
if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD &&
(cputype & 0x00000f00) == 0x00000600) {
cpufuncs = arm6_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 0;
get_cachetype_table();
pmap_pte_init_generic();
return 0;
@@ -1592,7 +1587,6 @@
CPU_ID_IS7(cputype) &&
(cputype & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V3) {
cpufuncs = arm7_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 0;
get_cachetype_table();
pmap_pte_init_generic();
return 0;
@@ -1603,7 +1597,6 @@
CPU_ID_IS7(cputype) &&
(cputype & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V4T) {
cpufuncs = arm7tdmi_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 0;
get_cachetype_cp15();
pmap_pte_init_generic();
return 0;
@@ -1613,7 +1606,6 @@
if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD &&
(cputype & 0x0000f000) == 0x00008000) {
cpufuncs = arm8_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 0; /* XXX correct? */
get_cachetype_cp15();
pmap_pte_init_arm8();
return 0;
@@ -1624,7 +1616,6 @@
(cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_TI) &&
(cputype & 0x0000f000) == 0x00009000) {
cpufuncs = arm9_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
get_cachetype_cp15();
arm9_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
arm9_dcache_sets_max =
@@ -1644,7 +1635,6 @@
if (cputype == CPU_ID_ARM926EJS ||
cputype == CPU_ID_ARM1026EJS) {
cpufuncs = armv5_ec_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
get_cachetype_cp15();
pmap_pte_init_generic();
return 0;
@@ -1654,7 +1644,6 @@
if (cputype == CPU_ID_MV88SV131 ||
cputype == CPU_ID_MV88FR571_VD) {
cpufuncs = sheeva_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
get_cachetype_cp15();
pmap_pte_init_generic();
cpu_do_powersave = 1; /* Enable powersave */
@@ -1669,7 +1658,6 @@
* option on ARM1020T).
*/
cpufuncs = arm10_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
get_cachetype_cp15();
armv5_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
armv5_dcache_sets_max =
@@ -1692,7 +1680,6 @@
arm_dcache_l2_nsets)) - armv5_dcache_sets_inc;
armv5_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc);
armv5_dcache_index_max = 0U - armv5_dcache_index_inc;
- cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
cpu_do_powersave = 1; /* Enable powersave */
pmap_pte_init_arm11mpcore();
if (arm_cache_prefer_mask)
@@ -1721,7 +1708,6 @@
cpufuncs = arm1176_cpufuncs;
}
#endif
- cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
cpu_do_powersave = 1; /* Enable powersave */
get_cachetype_cp15();
#ifdef ARM11_CACHE_WRITE_THROUGH
@@ -1738,7 +1724,6 @@
#ifdef CPU_SA110
if (cputype == CPU_ID_SA110) {
cpufuncs = sa110_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
get_cachetype_table();
pmap_pte_init_sa1();
return 0;
@@ -1747,7 +1732,6 @@
#ifdef CPU_SA1100
if (cputype == CPU_ID_SA1100) {
cpufuncs = sa11x0_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
get_cachetype_table();
pmap_pte_init_sa1();
@@ -1760,7 +1744,6 @@
#ifdef CPU_SA1110
if (cputype == CPU_ID_SA1110) {
cpufuncs = sa11x0_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
get_cachetype_table();
pmap_pte_init_sa1();
@@ -1773,7 +1756,6 @@
#ifdef CPU_FA526
if (cputype == CPU_ID_FA526) {
cpufuncs = fa526_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
get_cachetype_cp15();
pmap_pte_init_generic();
@@ -1786,7 +1768,6 @@
#ifdef CPU_IXP12X0
if (cputype == CPU_ID_IXP1200) {
cpufuncs = ixp12x0_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1;
get_cachetype_table();
pmap_pte_init_sa1();
return 0;
@@ -1843,7 +1824,6 @@
if (rev == 0 || rev == 1)
cpufuncs.cf_dcache_inv_range = xscale_cache_purgeD_rng;
- cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
get_cachetype_cp15();
pmap_pte_init_xscale();
return 0;
@@ -1872,7 +1852,6 @@
xscale_pmu_init();
#endif
- cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
get_cachetype_cp15();
pmap_pte_init_xscale();
return 0;
@@ -1889,7 +1868,6 @@
xscale_pmu_init();
#endif
- cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
get_cachetype_cp15();
pmap_pte_init_xscale();
@@ -1909,7 +1887,6 @@
xscale_pmu_init();
#endif
- cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
get_cachetype_cp15();
pmap_pte_init_xscale();
@@ -1919,7 +1896,6 @@
#if defined(CPU_CORTEX)
if (CPU_ID_CORTEX_P(cputype)) {
cpufuncs = cortex_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
cpu_do_powersave = 1; /* Enable powersave */
get_cachetype_cp15();
pmap_pte_init_armv7();
diff -r 149061c30371 -r dc4dc50eb384 sys/arch/arm/arm32/arm32_machdep.c
--- a/sys/arch/arm/arm32/arm32_machdep.c Thu Aug 16 18:16:25 2012 +0000
+++ b/sys/arch/arm/arm32/arm32_machdep.c Thu Aug 16 18:22:37 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: arm32_machdep.c,v 1.81 2012/08/16 17:35:01 matt Exp $ */
+/* $NetBSD: arm32_machdep.c,v 1.82 2012/08/16 18:22:39 matt Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@@ -42,7 +42,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.81 2012/08/16 17:35:01 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: arm32_machdep.c,v 1.82 2012/08/16 18:22:39 matt Exp $");
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