[src/trunk]: src/sys/arch/i386/include Fix spelling in comments, s/extention/...

[dyoung <dyoung%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/3ec1ce4081f7
branches:  trunk
changeset: 749106:3ec1ce4081f7
user:      dyoung <dyoung%NetBSD.org@localhost>
date:      Tue Nov 17 22:35:43 2009 +0000

description:
Fix spelling in comments, s/extention/extension/.

diffstat:

 sys/arch/i386/include/pte.h |  6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diffs (27 lines):

diff -r 490a376806f9 -r 3ec1ce4081f7 sys/arch/i386/include/pte.h
--- a/sys/arch/i386/include/pte.h       Tue Nov 17 22:20:14 2009 +0000
+++ b/sys/arch/i386/include/pte.h       Tue Nov 17 22:35:43 2009 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pte.h,v 1.19 2009/04/15 13:05:47 cegger Exp $  */
+/*     $NetBSD: pte.h,v 1.20 2009/11/17 22:35:43 dyoung Exp $  */
 
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
@@ -82,7 +82,7 @@
 #endif
 
 /*
- * i386 MMU hardware structure (without PAE extention):
+ * i386 MMU hardware structure (without PAE extension):
  *
  * the i386 MMU is a two-level MMU which maps 4GB of virtual memory.
  * the pagesize is 4K (4096 [0x1000] bytes), although newer pentium
@@ -162,7 +162,7 @@
  *    sense to flush these entries when switching from one process'
  *    pmap to another.
  *
- * The PAE extention extends the size of the PTE to 64 bits (52bits physical
+ * The PAE extension extends the size of the PTE to 64 bits (52bits physical
  * address) and is compatible with the amd64 PTE format. The first level
  * maps 2M, the second 1G, so a third level page table is intruduced to
  * map the 4GB virtual address space. This PD has only 4 entries.