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[src/netbsd-6]: src/sys/dev Pull up following revision(s) (requested by msait...
details: https://anonhg.NetBSD.org/src/rev/85a3494372be
branches: netbsd-6
changeset: 777053:85a3494372be
user: snj <snj%NetBSD.org@localhost>
date: Fri May 06 18:43:34 2016 +0000
description:
Pull up following revision(s) (requested by msaitoh in ticket #1366):
sys/dev/pci/if_wm.c: 1.281, 1.318, 1.320, 1.324-1.332, 1.334, 1.336, 1.343-1.344, 1.347-1.348, 1.350, 1.376-1.382, 1.386-1.387, 1.389 via patch
sys/dev/pci/if_wmreg.h: 1.68-1.70, 1.73-1.77, 1.79-1.80, 1.82, 1.86-1.88 via patch
sys/dev/pci/if_wmvar.h: 1.22-1.23, 1.25-1.30 via patch
sys/dev/mii/igphy.c: 1.25
sys/dev/mii/ukphy.c: 1.48
Sync wm(4) as of if_wm.c rev 1.389 except SERDES, MSI/MSI-X, multiqueue
and NET_MPSAFE:
- Set ICH9 and ICH10's PBA size to 14K if the RX buffer size is more
than 4096. Almost the same as other OSes.
- For 82576 and newer devices, the PBA register is deleted. Don't write
PBA for those chips. Also change the calculation of RX packet buffer
size in new way.
- Print NVM image version and option ROM version.
- Add workaround for I210 Errata 25 and I211 Errata 10 (PLL bug). This
workaround is required if the NVM image version < 3.25.
- Fix a bug that wm_detach() didn't unmap the FHASH's area. Now
"drvctl -d wm0" -> "drvctl -r pci0" works on ICH* and PCH*.
- Add workaround for 82574 Errata 25 and 82583 Errata 12 "Dropped RX
packets" and for 82573 (unknown). Set GCR_L1_ACT_WITHOUT_L0S_RX bit.
The NVM Image version 2.1.4 and newer have this workaround.
- Check PHY type correctly. This change is required to use igphy(4)
device correctly.
- Disable LPLU (Low Power Link Up) on D0 state on 82574, 82583 and ICH*
too.
- Call wm_get_hw_control() correctly. This change fixes a bug that some
AMT based systems doesn't linkup at 1000BaseT. The problem was
observed on HP Compaq dc7700. A lot of fixes have been done for wm(4)
and igphy(4), so now PR#44893 should be fixed.
- Call wm_get_wakeup(sc) before checking WM_F_HAS_AMT. It's required to
check the existence of AMT correctly.
- Fix a problem that wm_gate_hw_phy_config_ich8lan() isn't called in
wm_reset() on PCH2.
- Clear WMREG_WUC in wm_reset() if the chip >= 82544. This might fix
the behavior on suspend/resume.
- Fix logic of wm_check_reset_block() on ICH* and PCH*. This change
might fix a problem that PHY's read/write functions can't get
semaphore.
- On ICH8, call wm_gig_downshift_workaround_ich8lan() when link changed
down.
- Drop PHY_CTRL_GBE_DIS explicitly in wm_lplu_d0_disable() in case BIOS
sets this bit.
- Fix two bugs in wm_kmrn_lock_loss_workaround_ich8lan(). Now the
function checks the status correctly but it causes linkdown up to 10
times, so it's disabled for the time being.
- PR/50527: David Binderman: Fix impossible code. Odd offsets need
special treatment.
- Fix RAL table's size of PCH2 and PCH_LPT.
- PCH_LPT (and newer device) is required to check FWSM_WLOCK_MAC bit to
determine the range of the RAL.
- Use sc->sc_itr instead of hard-coded number.
- Rename wm_tbi_check_link() to wm_tbi_tick() because this function
acts as mii_tick().
- ACK Accelerate Disable in the RFCTL register is not bit 13 but 12.
No binary change because this definition has not used yet.
- Add ACK data Disable bit's definition (not used yet).
- PHY_CTRL_GBE_DIS is not bit 4 but bit 6. This change has no any
effect by default because WM_WOL is not defined yet and
m_kmrn_lock_loss_workaround_ich8lan() is broken.
- Fix wm_check_mng_mode_ich8lan(). This function is used only when
WM_WOL is defined and it's disabled by default.
- Rename wm_check_reset_block() to wm_phy_resetisblocked() and make it
returns bool. No functional change.
- Reorder function definitions and macro definitions. No functional
change.
- Fix comment. Add comment. Update comment.
- KNF.
diffstat:
sys/dev/mii/igphy.c | 7 +-
sys/dev/mii/ukphy.c | 7 +-
sys/dev/pci/if_wm.c | 840 +++++++++++++++++++++++++++++++++++++++---------
sys/dev/pci/if_wmreg.h | 104 +++++-
sys/dev/pci/if_wmvar.h | 72 ++-
5 files changed, 830 insertions(+), 200 deletions(-)
diffs (truncated from 1952 to 300 lines):
diff -r baa69fe318c2 -r 85a3494372be sys/dev/mii/igphy.c
--- a/sys/dev/mii/igphy.c Fri May 06 18:37:38 2016 +0000
+++ b/sys/dev/mii/igphy.c Fri May 06 18:43:34 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: igphy.c,v 1.21.16.1 2014/11/09 12:13:15 martin Exp $ */
+/* $NetBSD: igphy.c,v 1.21.16.2 2016/05/06 18:43:34 snj Exp $ */
/*
* The Intel copyright applies to the analog register setup, and the
@@ -70,7 +70,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: igphy.c,v 1.21.16.1 2014/11/09 12:13:15 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: igphy.c,v 1.21.16.2 2016/05/06 18:43:34 snj Exp $");
#include "opt_mii.h"
@@ -154,6 +154,9 @@
sc->mii_dev = self;
sc->mii_inst = mii->mii_instance;
sc->mii_phy = ma->mii_phyno;
+ sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
+ sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
+ sc->mii_mpd_rev = MII_REV(ma->mii_id2);
sc->mii_funcs = &igphy_funcs;
sc->mii_pdata = mii;
sc->mii_flags = ma->mii_flags;
diff -r baa69fe318c2 -r 85a3494372be sys/dev/mii/ukphy.c
--- a/sys/dev/mii/ukphy.c Fri May 06 18:37:38 2016 +0000
+++ b/sys/dev/mii/ukphy.c Fri May 06 18:43:34 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ukphy.c,v 1.43 2010/06/06 18:58:22 pgoyette Exp $ */
+/* $NetBSD: ukphy.c,v 1.43.14.1 2016/05/06 18:43:34 snj Exp $ */
/*-
* Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
@@ -59,7 +59,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ukphy.c,v 1.43 2010/06/06 18:58:22 pgoyette Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ukphy.c,v 1.43.14.1 2016/05/06 18:43:34 snj Exp $");
#include "opt_mii.h"
@@ -121,6 +121,9 @@
sc->mii_dev = self;
sc->mii_inst = mii->mii_instance;
sc->mii_phy = ma->mii_phyno;
+ sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
+ sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
+ sc->mii_mpd_rev = MII_REV(ma->mii_id2);
sc->mii_funcs = &ukphy_funcs;
sc->mii_pdata = mii;
sc->mii_flags = ma->mii_flags;
diff -r baa69fe318c2 -r 85a3494372be sys/dev/pci/if_wm.c
--- a/sys/dev/pci/if_wm.c Fri May 06 18:37:38 2016 +0000
+++ b/sys/dev/pci/if_wm.c Fri May 06 18:43:34 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.227.2.18 2015/04/30 19:53:28 snj Exp $ */
+/* $NetBSD: if_wm.c,v 1.227.2.19 2016/05/06 18:43:34 snj Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -72,11 +72,19 @@
*
* TODO (in order of importance):
*
+ * - Check XXX'ed comments
+ * - MSI/MSI-X
+ * - Disable D0 LPLU on 8257[12356], 82580 and I350.
+ * - Multi queue
+ * - EEE (Energy Efficiency Ethernet)
+ * - Image Unique ID
+ * - Virtual Function
+ * - Set LED correctly (based on contents in EEPROM)
* - Rework how parameters are loaded from the EEPROM.
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.227.2.18 2015/04/30 19:53:28 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.227.2.19 2016/05/06 18:43:34 snj Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -240,6 +248,10 @@
SWFW_PHY3_SM
};
+static const uint32_t wm_82580_rxpbs_table[] = {
+ 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140
+};
+
/*
* Software state per device.
*/
@@ -253,6 +265,7 @@
bus_size_t sc_ios; /* I/O space size */
bus_space_tag_t sc_flasht; /* flash registers space tag */
bus_space_handle_t sc_flashh; /* flash registers space handle */
+ bus_size_t sc_flashs; /* flash registers space size */
bus_dma_tag_t sc_dmat; /* bus DMA tag */
struct ethercom sc_ethercom; /* ethernet common data */
@@ -261,7 +274,7 @@
pci_chipset_tag_t sc_pc;
pcitag_t sc_pcitag;
int sc_bus_speed; /* PCI/PCIX bus speed */
- int sc_pcixe_capoff; /* PCI[Xe] capability register offset */
+ int sc_pcixe_capoff; /* PCI[Xe] capability reg offset */
const struct wm_product *sc_wmp; /* Pointer to the wm_product entry */
uint16_t sc_pcidevid; /* PCI device ID */
@@ -277,22 +290,21 @@
void *sc_ih; /* interrupt cookie */
callout_t sc_tick_ch; /* tick callout */
+ int sc_nvm_ver_major;
+ int sc_nvm_ver_minor;
+ int sc_nvm_ver_build;
int sc_nvm_addrbits; /* NVM address bits */
- unsigned int sc_nvm_wordsize; /* NVM word size */
+ unsigned int sc_nvm_wordsize; /* NVM word size */
int sc_ich8_flash_base;
int sc_ich8_flash_bank_size;
int sc_nvm_k1_enabled;
- /*
- * Software state for the transmit and receive descriptors.
- */
+ /* Software state for the transmit and receive descriptors. */
int sc_txnum; /* must be a power of two */
struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX];
struct wm_rxsoft sc_rxsoft[WM_NRXDESC];
- /*
- * Control data structures.
- */
+ /* Control data structures. */
int sc_ntxdesc; /* must be a power of two */
struct wm_control_data_82544 *sc_control_data;
bus_dmamap_t sc_cddmamap; /* control data DMA map */
@@ -532,6 +544,7 @@
static void wm_lan_init_done(struct wm_softc *);
static void wm_get_cfg_done(struct wm_softc *);
static void wm_initialize_hardware_bits(struct wm_softc *);
+static uint32_t wm_rxpbs_adjust_82580(uint32_t);
static void wm_reset(struct wm_softc *);
static int wm_add_rxbuf(struct wm_softc *, int);
static void wm_rxdrain(struct wm_softc *);
@@ -580,6 +593,8 @@
static void wm_gmii_hv_writereg(device_t, int, int, int);
static int wm_gmii_82580_readreg(device_t, int, int);
static void wm_gmii_82580_writereg(device_t, int, int, int);
+static int wm_gmii_gs40g_readreg(device_t, int, int);
+static void wm_gmii_gs40g_writereg(device_t, int, int, int);
static void wm_gmii_statchg(device_t);
static int wm_kmrn_readreg(struct wm_softc *, int);
static void wm_kmrn_writereg(struct wm_softc *, int, int);
@@ -621,11 +636,17 @@
static int32_t wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *);
static int32_t wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *);
static int wm_nvm_read_ich8(struct wm_softc *, int, int, uint16_t *);
+/* iNVM */
+static int wm_nvm_read_word_invm(struct wm_softc *, uint16_t, uint16_t *);
+static int wm_nvm_read_invm(struct wm_softc *, int, int, uint16_t *);
/* Lock, detecting NVM type, validate checksum and read */
static int wm_nvm_acquire(struct wm_softc *);
static void wm_nvm_release(struct wm_softc *);
static int wm_nvm_is_onboard_eeprom(struct wm_softc *);
+static int wm_nvm_get_flash_presence_i210(struct wm_softc *);
static int wm_nvm_validate_checksum(struct wm_softc *);
+static void wm_nvm_version_invm(struct wm_softc *);
+static void wm_nvm_version(struct wm_softc *);
static int wm_nvm_read(struct wm_softc *, int, int, uint16_t *);
/*
@@ -645,12 +666,14 @@
* Management mode and power management related subroutines.
* BMC, AMT, suspend/resume and EEE.
*/
+#ifdef WM_WOL
static int wm_check_mng_mode(struct wm_softc *);
static int wm_check_mng_mode_ich8lan(struct wm_softc *);
static int wm_check_mng_mode_82574(struct wm_softc *);
static int wm_check_mng_mode_generic(struct wm_softc *);
+#endif
static int wm_enable_mng_pass_thru(struct wm_softc *);
-static int wm_check_reset_block(struct wm_softc *);
+static bool wm_phy_resetisblocked(struct wm_softc *);
static void wm_get_hw_control(struct wm_softc *);
static void wm_release_hw_control(struct wm_softc *);
static void wm_gate_hw_phy_config_ich8lan(struct wm_softc *, int);
@@ -663,6 +686,9 @@
static void wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *);
static void wm_enable_wakeup(struct wm_softc *);
#endif
+/* LPLU (Low Power Link Up) */
+static void wm_lplu_d0_disable(struct wm_softc *);
+static void wm_lplu_d0_disable_pch(struct wm_softc *);
/* EEE */
static void wm_set_eee_i350(struct wm_softc *);
@@ -678,6 +704,7 @@
static void wm_set_mdio_slow_mode_hv(struct wm_softc *);
static void wm_configure_k1_ich8lan(struct wm_softc *, int);
static void wm_reset_init_script_82575(struct wm_softc *);
+static void wm_pll_workaround_i210(struct wm_softc *);
CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc),
wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
@@ -1642,9 +1669,7 @@
goto fail_3;
}
- /*
- * Create the transmit buffer DMA maps.
- */
+ /* Create the transmit buffer DMA maps. */
WM_TXQUEUELEN(sc) =
(sc->sc_type == WM_T_82547 || sc->sc_type == WM_T_82547_2) ?
WM_TXQUEUELEN_MAX_82547 : WM_TXQUEUELEN_MAX;
@@ -1659,9 +1684,7 @@
}
}
- /*
- * Create the receive buffer DMA maps.
- */
+ /* Create the receive buffer DMA maps. */
for (i = 0; i < WM_NRXDESC; i++) {
if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
MCLBYTES, 0, 0,
@@ -1683,14 +1706,10 @@
|| (sc->sc_type == WM_T_PCH_LPT))
wm_smbustopci(sc);
- /*
- * Reset the chip to a known state.
- */
+ /* Reset the chip to a known state. */
wm_reset(sc);
- /*
- * Get some information about the EEPROM.
- */
+ /* Get some information about the EEPROM. */
switch (sc->sc_type) {
case WM_T_82542_2_0:
case WM_T_82542_2_1:
@@ -1714,13 +1733,13 @@
sc->sc_nvm_wordsize = 64;
sc->sc_nvm_addrbits = 6;
}
- sc->sc_flags |= WM_F_EEPROM_HANDSHAKE;
+ sc->sc_flags |= WM_F_LOCK_EECD;
break;
case WM_T_82541:
case WM_T_82541_2:
case WM_T_82547:
case WM_T_82547_2:
- sc->sc_flags |= WM_F_EEPROM_HANDSHAKE;
+ sc->sc_flags |= WM_F_LOCK_EECD;
reg = CSR_READ(sc, WMREG_EECD);
if (reg & EECD_EE_TYPE) {
/* SPI */
@@ -1742,11 +1761,11 @@
/* SPI */
sc->sc_flags |= WM_F_EEPROM_SPI;
wm_nvm_set_addrbits_size_eecd(sc);
- sc->sc_flags |= WM_F_EEPROM_SEMAPHORE;
- sc->sc_flags |= WM_F_EEPROM_HANDSHAKE;
+ sc->sc_flags |= WM_F_LOCK_SWSM;
+ sc->sc_flags |= WM_F_LOCK_EECD;
break;
case WM_T_82573:
- sc->sc_flags |= WM_F_EEPROM_SEMAPHORE;
+ sc->sc_flags |= WM_F_LOCK_SWSM;
/* FALLTHROUGH */
case WM_T_82574:
case WM_T_82583:
@@ -1769,8 +1788,8 @@
/* SPI */
sc->sc_flags |= WM_F_EEPROM_SPI;
wm_nvm_set_addrbits_size_eecd(sc);
- sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_SWFW_SYNC
- | WM_F_EEPROM_SEMAPHORE;
+ sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_LOCK_SWFW
+ | WM_F_LOCK_SWSM;
break;
case WM_T_ICH8:
case WM_T_ICH9:
@@ -1779,11 +1798,11 @@
case WM_T_PCH2:
case WM_T_PCH_LPT:
/* FLASH */
- sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_SWFWHW_SYNC;
+ sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_LOCK_EXTCNF;
sc->sc_nvm_wordsize = 2048;
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