[src/trunk]: src/sys/arch/sparc64 define MANUF_FUJITSU (and fix CPU_IS_SPARC6...

[mrg <mrg%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/594e7b4e7768
branches:  trunk
changeset: 765399:594e7b4e7768
user:      mrg <mrg%NetBSD.org@localhost>
date:      Wed May 25 12:01:30 2011 +0000

description:
define MANUF_FUJITSU (and fix CPU_IS_SPARC64_V_UP()) and MANUF_SUN.

use CPU_IS_SPARC64_V_UP() to choose some US-III versions of some
cache functions.

diffstat:

 sys/arch/sparc64/include/psl.h   |   5 ++++-
 sys/arch/sparc64/sparc64/cache.h |  10 ++++++----
 2 files changed, 10 insertions(+), 5 deletions(-)

diffs (64 lines):

diff -r 5f9b6cd7266e -r 594e7b4e7768 sys/arch/sparc64/include/psl.h
--- a/sys/arch/sparc64/include/psl.h    Wed May 25 06:13:29 2011 +0000
+++ b/sys/arch/sparc64/include/psl.h    Wed May 25 12:01:30 2011 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: psl.h,v 1.47 2011/05/12 05:42:05 mrg Exp $ */
+/*     $NetBSD: psl.h,v 1.48 2011/05/25 12:01:30 mrg Exp $ */
 
 /*
  * Copyright (c) 1992, 1993
@@ -224,6 +224,9 @@
 #define VER_MAXTL_SHIFT        8
 #define VER_MAXWIN     0x000000000000001fLL
 
+#define MANUF_FUJITSU          0x04 /* Fujitsu SPARC64 */
+#define MANUF_SUN              0x17 /* Sun UltraSPARC */
+
 #define IMPL_SPARC64           0x01 /* SPARC64 */
 #define IMPL_SPARC64_II                0x02 /* SPARC64-II */
 #define IMPL_SPARC64_III       0x03 /* SPARC64-III */
diff -r 5f9b6cd7266e -r 594e7b4e7768 sys/arch/sparc64/sparc64/cache.h
--- a/sys/arch/sparc64/sparc64/cache.h  Wed May 25 06:13:29 2011 +0000
+++ b/sys/arch/sparc64/sparc64/cache.h  Wed May 25 12:01:30 2011 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache.h,v 1.19 2011/05/12 05:42:42 mrg Exp $ */
+/*     $NetBSD: cache.h,v 1.20 2011/05/25 12:01:31 mrg Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -72,6 +72,8 @@
  * set-associative -- each bank is 8K.  No conflict there.)
  */
 
+#include <machine/psl.h>
+
 /* Various cache size/line sizes */
 extern int     ecache_min_line_size;
 extern int     dcache_line_size;
@@ -104,7 +106,7 @@
 static __inline__ void
 cache_flush_phys(paddr_t pa, psize_t size, int ecache)
 {
-       if (CPU_IS_USIII_UP())
+       if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP())
                cache_flush_phys_usiii(pa, size, ecache);
        else
                cache_flush_phys_us(pa, size, ecache);
@@ -131,7 +133,7 @@
 static __inline__ void
 sp_tlb_flush_pte(vaddr_t va, int ctx)
 {
-       if (CPU_IS_USIII_UP())
+       if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP())
                sp_tlb_flush_pte_usiii(va, ctx);
        else
                sp_tlb_flush_pte_us(va, ctx);
@@ -140,7 +142,7 @@
 static __inline__ void
 sp_tlb_flush_all(void)
 {
-       if (CPU_IS_USIII_UP())
+       if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP())
                sp_tlb_flush_all_usiii();
        else
                sp_tlb_flush_all_us();